[CSKY] Add floating operation support including float and double

CSKY arch has multiple FPU instruction versions such as FPU, FPUv2 and FPUv3 to implement floating operations. For now, we just only support FPUv2 and FPUv3. It includes the encoding, asm parsing of instructions and codegen of DAG nodes.
llvm · Jan 27, 2022 · 4ad517e · 4ad517e
1 parent 615d71d
commit 4ad517e
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Showing 28 changed files with 8,490 additions and 8 deletions.
diff --git a/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp b/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
@@ -303,6 +303,14 @@ struct CSKYOperand : public MCParsedAsmOperand {
 
   bool isRegSeq() const { return isRegSeqTemplate<CSKY::R0, CSKY::R31>(); }
 
+  bool isRegSeqV1() const {
+    return isRegSeqTemplate<CSKY::F0_32, CSKY::F15_32>();
+  }
+
+  bool isRegSeqV2() const {
+    return isRegSeqTemplate<CSKY::F0_32, CSKY::F31_32>();
+  }
+
   static bool isLegalRegList(unsigned from, unsigned to) {
     if (from == 0 && to == 0)
       return true;

diff --git a/llvm/lib/Target/CSKY/CSKY.td b/llvm/lib/Target/CSKY/CSKY.td
@@ -11,6 +11,40 @@ include "llvm/Target/Target.td"
 //===----------------------------------------------------------------------===//
 // CSKY subtarget features and instruction predicates.
 //===----------------------------------------------------------------------===//
+def ModeHardFloat :
+  SubtargetFeature<"hard-float", "UseHardFloat",
+                   "true", "Use hard floating point features">;
+def ModeHardFloatABI :
+  SubtargetFeature<"hard-float-abi", "UseHardFloatABI",
+                   "true", "Use hard floating point ABI to pass args">;
+
+def FeatureFPUV2_SF
+    : SubtargetFeature<"fpuv2_sf", "HasFPUv2SingleFloat", "true",
+                       "Enable FPUv2 single float instructions">;
+def HasFPUv2_SF : Predicate<"Subtarget->hasFPUv2SingleFloat()">,
+                  AssemblerPredicate<(all_of FeatureFPUV2_SF),
+                  "Enable FPUv2 single float instructions">;
+
+def FeatureFPUV2_DF
+    : SubtargetFeature<"fpuv2_df", "HasFPUv2DoubleFloat", "true",
+                       "Enable FPUv2 double float instructions">;
+def HasFPUv2_DF : Predicate<"Subtarget->hasFPUv2DoubleFloat()">,
+                  AssemblerPredicate<(all_of FeatureFPUV2_DF),
+                  "Enable FPUv2 double float instructions">;
+
+def FeatureFPUV3_SF
+    : SubtargetFeature<"fpuv3_sf", "HasFPUv3SingleFloat", "true",
+                       "Enable FPUv3 single float instructions">;
+def HasFPUv3_SF : Predicate<"Subtarget->hasFPUv3SingleFloat()">,
+                  AssemblerPredicate<(all_of FeatureFPUV3_SF),
+                  "Enable FPUv3 single float instructions">;
+
+def FeatureFPUV3_DF
+    : SubtargetFeature<"fpuv3_df", "HasFPUv3DoubleFloat", "true",
+                       "Enable FPUv3 double float instructions">;
+def HasFPUv3_DF : Predicate<"Subtarget->hasFPUv3DoubleFloat()">,
+                  AssemblerPredicate<(all_of FeatureFPUV3_DF),
+                  "Enable FPUv3 double float instructions">;
 
 def FeatureBTST16 : SubtargetFeature<"btst16", "HasBTST16", "true",
                                      "Use the 16-bit btsti instruction">;

diff --git a/llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp b/llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp
@@ -551,6 +551,11 @@ void CSKYConstantIslands::initializeFunctionInfo(
             Bits = 16;
             Scale = 4;
             break;
+          case CSKY::f2FLRW_S:
+          case CSKY::f2FLRW_D:
+            Bits = 8;
+            Scale = 4;
+            break;
           case CSKY::GRS32:
             Bits = 17;
             Scale = 2;

diff --git a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
@@ -38,6 +38,18 @@ CSKYTargetLowering::CSKYTargetLowering(const TargetMachine &TM,
   // Register Class
   addRegisterClass(MVT::i32, &CSKY::GPRRegClass);
 
+  if (STI.useHardFloat()) {
+    if (STI.hasFPUv2SingleFloat())
+      addRegisterClass(MVT::f32, &CSKY::sFPR32RegClass);
+    else if (STI.hasFPUv3SingleFloat())
+      addRegisterClass(MVT::f32, &CSKY::FPR32RegClass);
+
+    if (STI.hasFPUv2DoubleFloat())
+      addRegisterClass(MVT::f64, &CSKY::sFPR64RegClass);
+    else if (STI.hasFPUv3DoubleFloat())
+      addRegisterClass(MVT::f64, &CSKY::FPR64RegClass);
+  }
+
   setOperationAction(ISD::ADDCARRY, MVT::i32, Legal);
   setOperationAction(ISD::SUBCARRY, MVT::i32, Legal);
   setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
@@ -95,6 +107,40 @@ CSKYTargetLowering::CSKYTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
   }
 
+  // Float
+
+  ISD::CondCode FPCCToExtend[] = {
+      ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
+      ISD::SETUGE, ISD::SETULT, ISD::SETULE,
+  };
+
+  ISD::NodeType FPOpToExpand[] = {ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
+                                  ISD::FPOW, ISD::FREM, ISD::FCOPYSIGN};
+
+  if (STI.useHardFloat()) {
+
+    MVT AllVTy[] = {MVT::f32, MVT::f64};
+
+    for (auto VT : AllVTy) {
+      setOperationAction(ISD::FREM, VT, Expand);
+      setOperationAction(ISD::SELECT_CC, VT, Expand);
+      setOperationAction(ISD::BR_CC, VT, Expand);
+
+      for (auto CC : FPCCToExtend)
+        setCondCodeAction(CC, VT, Expand);
+      for (auto Op : FPOpToExpand)
+        setOperationAction(Op, VT, Expand);
+    }
+
+    if (STI.hasFPUv2SingleFloat() || STI.hasFPUv3SingleFloat()) {
+      setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
+    }
+    if (STI.hasFPUv2DoubleFloat() || STI.hasFPUv3DoubleFloat()) {
+      setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
+      setTruncStoreAction(MVT::f64, MVT::f32, Expand);
+    }
+  }
+
   // Compute derived properties from the register classes.
   computeRegisterProperties(STI.getRegisterInfo());