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[MSVC, ARM64] Add __readx18 intrinsics
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https://docs.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-170

  unsigned char __readx18byte(unsigned long)
  unsigned short __readx18word(unsigned long)
  unsigned long __readx18dword(unsigned long)
  unsigned __int64 __readx18qword(unsigned long)

Given the lack of documentation of the intrinsics, we chose to align the offset with just
`CharUnits::One()` when calling `IRBuilderBase::CreateAlignedLoad()`

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D126024
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@steplong
steplong committed May 23, 2022
1 parent 0da230f commit 4f1e64b
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Showing 4 changed files with 93 additions and 0 deletions.
5 changes: 5 additions & 0 deletions clang/include/clang/Basic/BuiltinsAArch64.def
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Expand Up @@ -256,6 +256,11 @@ TARGET_HEADER_BUILTIN(__writex18word, "vULiUs", "nh", "intrin.h", ALL_MS_LANGUA
TARGET_HEADER_BUILTIN(__writex18dword, "vULiULi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__writex18qword, "vULiULLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")

TARGET_HEADER_BUILTIN(__readx18byte, "UcULi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__readx18word, "UsULi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__readx18dword, "ULiULi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__readx18qword, "ULLiULi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")

#undef BUILTIN
#undef LANGBUILTIN
#undef TARGET_HEADER_BUILTIN
24 changes: 24 additions & 0 deletions clang/lib/CodeGen/CGBuiltin.cpp
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Expand Up @@ -9977,6 +9977,30 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
return Store;
}

if (BuiltinID == AArch64::BI__readx18byte ||
BuiltinID == AArch64::BI__readx18word ||
BuiltinID == AArch64::BI__readx18dword ||
BuiltinID == AArch64::BI__readx18qword) {
llvm::Type *IntTy = ConvertType(E->getType());

// Read x18 as i8*
LLVMContext &Context = CGM.getLLVMContext();
llvm::Metadata *Ops[] = {llvm::MDString::get(Context, "x18")};
llvm::MDNode *RegName = llvm::MDNode::get(Context, Ops);
llvm::Value *Metadata = llvm::MetadataAsValue::get(Context, RegName);
llvm::Function *F =
CGM.getIntrinsic(llvm::Intrinsic::read_register, {Int64Ty});
llvm::Value *X18 = Builder.CreateCall(F, Metadata);
X18 = Builder.CreateIntToPtr(X18, llvm::PointerType::get(Int8Ty, 0));

// Load x18 + offset
Value *Offset = Builder.CreateZExt(EmitScalarExpr(E->getArg(0)), Int64Ty);
Value *Ptr = Builder.CreateGEP(Int8Ty, X18, Offset);
Ptr = Builder.CreatePointerCast(Ptr, llvm::PointerType::get(IntTy, 0));
LoadInst *Load = Builder.CreateAlignedLoad(IntTy, Ptr, CharUnits::One());
return Load;
}

// Handle MSVC intrinsics before argument evaluation to prevent double
// evaluation.
if (Optional<MSVCIntrin> MsvcIntId = translateAarch64ToMsvcIntrin(BuiltinID))
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5 changes: 5 additions & 0 deletions clang/lib/Headers/intrin.h
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Expand Up @@ -567,6 +567,11 @@ void __writex18byte(unsigned long offset, unsigned char data);
void __writex18word(unsigned long offset, unsigned short data);
void __writex18dword(unsigned long offset, unsigned long data);
void __writex18qword(unsigned long offset, unsigned __int64 data);

unsigned char __readx18byte(unsigned long offset);
unsigned short __readx18word(unsigned long offset);
unsigned long __readx18dword(unsigned long offset);
unsigned __int64 __readx18qword(unsigned long offset);
#endif

/*----------------------------------------------------------------------------*\
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59 changes: 59 additions & 0 deletions clang/test/CodeGen/arm64-microsoft-intrinsics.c
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Expand Up @@ -187,5 +187,64 @@ void check__writex18qword(unsigned long offset, unsigned __int64 data) {
// CHECK-MSVC: %[[DATA:.*]] = load i64, i64* %[[DATA_ADDR]], align 8
// CHECK-MSVC: store i64 %[[DATA]], i64* %[[BITCAST_PTR]], align 1

unsigned char check__readx18byte(unsigned long offset) {
return __readx18byte(offset);
}

// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
// CHECK-MSVC: store i32 %offset, i32* %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to i8*
// CHECK-MSVC: %[[OFFSET:.*]] = load i32, i32* %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, i8* %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
// CHECK-MSVC: %[[RETVAL:.*]] = load i8, i8* %[[PTR]], align 1
// CHECK-MSVC: ret i8 %[[RETVAL]]

unsigned short check__readx18word(unsigned long offset) {
return __readx18word(offset);
}

// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
// CHECK-MSVC: store i32 %offset, i32* %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to i8*
// CHECK-MSVC: %[[OFFSET:.*]] = load i32, i32* %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, i8* %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
// CHECK-MSVC: %[[BITCAST_PTR:.*]] = bitcast i8* %[[PTR]] to i16*
// CHECK-MSVC: %[[RETVAL:.*]] = load i16, i16* %[[BITCAST_PTR]], align 1
// CHECK-MSVC: ret i16 %[[RETVAL]]

unsigned long check__readx18dword(unsigned long offset) {
return __readx18dword(offset);
}

// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
// CHECK-MSVC: store i32 %offset, i32* %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to i8*
// CHECK-MSVC: %[[OFFSET:.*]] = load i32, i32* %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, i8* %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
// CHECK-MSVC: %[[BITCAST_PTR:.*]] = bitcast i8* %[[PTR]] to i32*
// CHECK-MSVC: %[[RETVAL:.*]] = load i32, i32* %[[BITCAST_PTR]], align 1
// CHECK-MSVC: ret i32 %[[RETVAL]]

unsigned __int64 check__readx18qword(unsigned long offset) {
return __readx18qword(offset);
}

// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
// CHECK-MSVC: store i32 %offset, i32* %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to i8*
// CHECK-MSVC: %[[OFFSET:.*]] = load i32, i32* %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, i8* %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
// CHECK-MSVC: %[[BITCAST_PTR:.*]] = bitcast i8* %[[PTR]] to i64*
// CHECK-MSVC: %[[RETVAL:.*]] = load i64, i64* %[[BITCAST_PTR]], align 1
// CHECK-MSVC: ret i64 %[[RETVAL]]

// CHECK-MSVC: ![[MD2]] = !{!"x18"}
// CHECK-MSVC: ![[MD3]] = !{!"sp"}

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