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[AMDGPU] Sort out and rename multiple CI/VI predicates
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Differential Revision: https://reviews.llvm.org/D60346

llvm-svn: 357835
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@rampitec
rampitec committed Apr 6, 2019
1 parent 4be8629 commit 5182302
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Showing 14 changed files with 82 additions and 85 deletions.
17 changes: 11 additions & 6 deletions llvm/lib/Target/AMDGPU/AMDGPU.td
View file
Expand Up @@ -689,7 +689,7 @@ def isGFX6GFX7 :
"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
AssemblerPredicate<"!FeatureGCN3Encoding">;

def isGFX7 :
def isGFX7Only :
Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
AssemblerPredicate<"!FeatureGCN3Encoding,FeatureCIInsts">;

Expand All @@ -707,18 +707,23 @@ def isGFX8Plus :
Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
AssemblerPredicate<"FeatureGFX8Insts">;

def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
"AMDGPUSubtarget::VOLCANIC_ISLANDS">,
AssemblerPredicate <"FeatureVolcanicIslands">;

def isGFX9Plus :
Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
AssemblerPredicate<"FeatureGFX9Insts">;

def isVI : Predicate <
"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
AssemblerPredicate<"FeatureGCN3Encoding">;

def isGFX9 : Predicate <
def isGFX9Only : Predicate <
"Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
AssemblerPredicate<"FeatureGCN3Encoding,FeatureGFX9Insts">;

def isGFX8GFX9 :
Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
"Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
AssemblerPredicate<"FeatureGFX8Insts,FeatureGCN3Encoding">;

def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
AssemblerPredicate<"FeatureFlatAddressSpace">;

Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/Target/AMDGPU/BUFInstructions.td
View file
Expand Up @@ -830,7 +830,7 @@ defm BUFFER_LOAD_DWORDX4 : MUBUF_Pseudo_Loads <
// This is not described in AMD documentation,
// but 'lds' versions of these opcodes are available
// in at least GFX8+ chips. See Bug 37653.
let SubtargetPredicate = isVI in {
let SubtargetPredicate = isGFX8GFX9 in {
defm BUFFER_LOAD_DWORDX2_LDS : MUBUF_Pseudo_Loads <
"buffer_load_dwordx2", VReg_64, v2i32, null_frag, 0, 1
>;
Expand Down Expand Up @@ -939,7 +939,7 @@ defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Pseudo_Atomics <
"buffer_atomic_dec_x2", VReg_64, i64, atomic_dec_global
>;

let SubtargetPredicate = isVI in {
let SubtargetPredicate = isGFX8GFX9 in {
def BUFFER_STORE_LDS_DWORD : MUBUF_Pseudo_Store_Lds <"buffer_store_lds_dword">;
}

Expand Down Expand Up @@ -1804,8 +1804,8 @@ defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Real_AllAddr_si <7>;

class MUBUF_Real_ci <bits<7> op, MUBUF_Pseudo ps> :
MUBUF_Real_si<op, ps> {
let AssemblerPredicate=isCIOnly;
let DecoderNamespace="GFX7";
let AssemblerPredicate = isGFX7Only;
let DecoderNamespace = "GFX7";
}

def BUFFER_WBINVL1_VOL_ci : MUBUF_Real_ci <0x70, BUFFER_WBINVL1_VOL>;
Expand All @@ -1819,8 +1819,8 @@ class MUBUF_Real_vi <bits<7> op, MUBUF_Pseudo ps> :
MUBUF_Real<op, ps>,
Enc64,
SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI> {
let AssemblerPredicate=isVI;
let DecoderNamespace="VI";
let AssemblerPredicate = isGFX8GFX9;
let DecoderNamespace = "GFX8";

let Inst{11-0} = !if(ps.has_offset, offset, ?);
let Inst{12} = ps.offen;
Expand Down Expand Up @@ -1994,8 +1994,8 @@ class MTBUF_Real_vi <bits<4> op, MTBUF_Pseudo ps> :
MTBUF_Real<ps>,
Enc64,
SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI> {
let AssemblerPredicate=isVI;
let DecoderNamespace="VI";
let AssemblerPredicate = isGFX8GFX9;
let DecoderNamespace = "GFX8";

let Inst{11-0} = !if(ps.has_offset, offset, ?);
let Inst{12} = ps.offen;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/DSInstructions.td
View file
Expand Up @@ -985,8 +985,8 @@ def DS_READ_B128_si : DS_Real_si<0xff, DS_READ_B128>;
class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
DS_Real <ds>,
SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
let AssemblerPredicates = [isVI];
let DecoderNamespace="VI";
let AssemblerPredicates = [isGFX8GFX9];
let DecoderNamespace = "GFX8";

// encoding
let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
View file
Expand Up @@ -226,7 +226,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
// Try decode 32-bit instruction
if (Bytes.size() < 4) break;
const uint32_t DW = eatBytes<uint32_t>(Bytes);
Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address);
Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
if (Res) break;

Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
Expand All @@ -237,7 +237,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,

if (Bytes.size() < 4) break;
const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);
Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
if (Res) break;

Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/AMDGPU/FLATInstructions.td
View file
Expand Up @@ -493,7 +493,7 @@ defm FLAT_ATOMIC_DEC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_dec_x2",
VReg_64, i64, atomic_dec_flat>;

// GFX7-only flat instructions.
let SubtargetPredicate = isGFX7 in {
let SubtargetPredicate = isGFX7Only in {

defm FLAT_ATOMIC_FCMPSWAP : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap",
VGPR_32, f32, null_frag, v2f32, VReg_64>;
Expand All @@ -513,7 +513,7 @@ defm FLAT_ATOMIC_FMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmin_x2",
defm FLAT_ATOMIC_FMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmax_x2",
VReg_64, f64>;

} // End SubtargetPredicate = isGFX7
} // End SubtargetPredicate = isGFX7Only

let SubtargetPredicate = HasFlatGlobalInsts in {
defm GLOBAL_LOAD_UBYTE : FLAT_Global_Load_Pseudo <"global_load_ubyte", VGPR_32>;
Expand Down Expand Up @@ -892,7 +892,7 @@ def : FlatSignedAtomicPat <GLOBAL_ATOMIC_XOR_X2_RTN, atomic_xor_global, i64>;
class FLAT_Real_ci <bits<7> op, FLAT_Pseudo ps> :
FLAT_Real <op, ps>,
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SI> {
let AssemblerPredicate = isCIOnly;
let AssemblerPredicate = isGFX7Only;
let DecoderNamespace="GFX7";
}

Expand Down Expand Up @@ -960,8 +960,8 @@ defm FLAT_ATOMIC_FMAX_X2 : FLAT_Real_Atomics_ci <0x60, FLAT_ATOMIC_FMAX_X2
class FLAT_Real_vi <bits<7> op, FLAT_Pseudo ps> :
FLAT_Real <op, ps>,
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.VI> {
let AssemblerPredicate = isVI;
let DecoderNamespace="VI";
let AssemblerPredicate = isGFX8GFX9;
let DecoderNamespace = "GFX8";
}

multiclass FLAT_Real_AllAddr_vi<bits<7> op> {
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/MIMGInstructions.td
View file
Expand Up @@ -267,10 +267,10 @@ multiclass MIMG_Atomic_Helper_m <mimg op, string asm, RegisterClass data_rc,
let DisableDecoder = DisableSIDecoder;
}

def _vi : MIMG_Atomic_Helper<asm, data_rc, addr_rc, "VI", enableDasm>,
def _vi : MIMG_Atomic_Helper<asm, data_rc, addr_rc, "GFX8", enableDasm>,
SIMCInstr<NAME, SIEncodingFamily.VI>,
MIMGe<op.VI> {
let AssemblerPredicates = [isVI];
let AssemblerPredicates = [isGFX8GFX9];
let DisableDecoder = DisableVIDecoder;
let MIMGEncoding = MIMGEncGfx8;
}
Expand Down
16 changes: 4 additions & 12 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
View file
Expand Up @@ -5,20 +5,12 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
def isCI : Predicate<"Subtarget->getGeneration() "
">= AMDGPUSubtarget::SEA_ISLANDS">;
def isCIOnly : Predicate<"Subtarget->getGeneration() =="
"AMDGPUSubtarget::SEA_ISLANDS">,
AssemblerPredicate <"FeatureSeaIslands">;
def isVIOnly : Predicate<"Subtarget->getGeneration() =="
"AMDGPUSubtarget::VOLCANIC_ISLANDS">,
AssemblerPredicate <"FeatureVolcanicIslands">;

def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;

class GCNPredicateControl : PredicateControl {
Predicate SIAssemblerPredicate = isGFX6GFX7;
Predicate VIAssemblerPredicate = isVI;
Predicate VIAssemblerPredicate = isGFX8GFX9;
}

// Execpt for the NONE field, this must be kept in sync with the
Expand Down Expand Up @@ -1157,8 +1149,8 @@ multiclass EXP_m<bit done, SDPatternOperator node> {
def _vi : EXP_Helper<done>,
SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.VI>,
EXPe_vi {
let AssemblerPredicates = [isVI];
let DecoderNamespace = "VI";
let AssemblerPredicates = [isGFX8GFX9];
let DecoderNamespace = "GFX8";
let DisableDecoder = DisableVIDecoder;
}
}
Expand Down Expand Up @@ -2016,7 +2008,7 @@ class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
VINTRPe_vi <op>,
SIMCInstr<opName, SIEncodingFamily.VI> {
let AssemblerPredicate = VIAssemblerPredicate;
let DecoderNamespace = "VI";
let DecoderNamespace = "GFX8";
let DisableDecoder = DisableVIDecoder;
}

Expand Down
18 changes: 9 additions & 9 deletions llvm/lib/Target/AMDGPU/SMInstructions.td
View file
Expand Up @@ -375,7 +375,7 @@ defm S_ATOMIC_DEC_X2 : SM_Pseudo_Atomics <"s_atomic_dec_x2", SReg_6

} // let SubtargetPredicate = HasScalarAtomics

let SubtargetPredicate = isGFX9 in {
let SubtargetPredicate = isGFX9Only in {
defm S_DCACHE_DISCARD : SM_Pseudo_Discards <"s_dcache_discard">;
defm S_DCACHE_DISCARD_X2 : SM_Pseudo_Discards <"s_dcache_discard_x2">;
}
Expand Down Expand Up @@ -447,8 +447,8 @@ class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
, Enc64 {
bit glc;

let AssemblerPredicates = [isVI];
let DecoderNamespace = "VI";
let AssemblerPredicates = [isGFX8GFX9];
let DecoderNamespace = "GFX8";

let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?);
Expand Down Expand Up @@ -636,7 +636,7 @@ class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> :
SM_Real<ps>,
Enc64 {

let AssemblerPredicates = [isGFX7];
let AssemblerPredicates = [isGFX7Only];
let DecoderNamespace = "GFX7";
let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, GLC:$glc);

Expand Down Expand Up @@ -673,7 +673,7 @@ class SMRD_Real_ci <bits<5> op, SM_Pseudo ps>
, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
, Enc32 {

let AssemblerPredicates = [isGFX7];
let AssemblerPredicates = [isGFX7Only];
let DecoderNamespace = "GFX7";

let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?);
Expand Down Expand Up @@ -725,7 +725,7 @@ multiclass SMRD_Pattern <string Instr, ValueType vt> {
def : GCNPat <
(smrd_load (SMRDImm32 i64:$sbase, i32:$offset)),
(vt (!cast<InstSI>(Instr#"_IMM_ci") $sbase, $offset, 0))> {
let OtherPredicates = [isGFX7];
let OtherPredicates = [isGFX7Only];
}

// 3. SGPR offset
Expand All @@ -752,7 +752,7 @@ multiclass SMLoad_Pattern <string Instr, ValueType vt> {
def : GCNPat <
(vt (SIsbuffer_load v4i32:$sbase, (SMRDBufferImm32 i32:$offset), i1:$glc)),
(!cast<InstSI>(Instr#"_IMM_ci") $sbase, $offset, (as_i1imm $glc))> {
let OtherPredicates = [isCIOnly];
let OtherPredicates = [isGFX7Only];
}

// 3. Offset loaded in an 32bit SGPR
Expand Down Expand Up @@ -793,11 +793,11 @@ def : GCNPat <
>;
}

let OtherPredicates = [isVI] in {
let OtherPredicates = [isGFX8Plus] in {

def : GCNPat <
(i64 (readcyclecounter)),
(S_MEMREALTIME)
>;

} // let OtherPredicates = [isVI]
} // let OtherPredicates = [isGFX8Plus]
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/SOPInstructions.td
View file
Expand Up @@ -526,7 +526,7 @@ let Defs = [SCC] in {
def S_ABSDIFF_I32 : SOP2_32 <"s_absdiff_i32">;
} // End Defs = [SCC]

let SubtargetPredicate = isVI in {
let SubtargetPredicate = isGFX8GFX9 in {
def S_RFE_RESTORE_B64 : SOP2_Pseudo <
"s_rfe_restore_b64", (outs),
(ins SSrc_b64:$src0, SSrc_b32:$src1),
Expand Down Expand Up @@ -1261,8 +1261,8 @@ def S_SETREG_IMM32_B32_si : SOPK_Real64<0x15, S_SETREG_IMM32_B32>,

class Select_vi<string opName> :
SIMCInstr<opName, SIEncodingFamily.VI> {
list<Predicate> AssemblerPredicates = [isVI];
string DecoderNamespace = "VI";
list<Predicate> AssemblerPredicates = [isGFX8GFX9];
string DecoderNamespace = "GFX8";
}

class SOP1_Real_vi<bits<8> op, SOP1_Pseudo ps> :
Expand Down
18 changes: 9 additions & 9 deletions llvm/lib/Target/AMDGPU/VOP1Instructions.td
View file
Expand Up @@ -405,9 +405,9 @@ let SubtargetPredicate = isGFX9Plus in {
defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16>;
} // End SubtargetPredicate = isGFX9Plus

let SubtargetPredicate = isGFX9 in {
let SubtargetPredicate = isGFX9Only in {
defm V_SCREEN_PARTITION_4SE_B32 : VOP1Inst <"v_screen_partition_4se_b32", VOP_I32_I32>;
} // End SubtargetPredicate = isGFX9
} // End SubtargetPredicate = isGFX9Only

//===----------------------------------------------------------------------===//
// Target
Expand Down Expand Up @@ -493,7 +493,7 @@ defm V_MOVRELSD_B32 : VOP1_Real_si <0x44>;
//===----------------------------------------------------------------------===//

multiclass VOP1_Real_ci <bits<9> op> {
let AssemblerPredicates = [isCIOnly], DecoderNamespace = "GFX7" in {
let AssemblerPredicates = [isGFX7Only], DecoderNamespace = "GFX7" in {
def _e32_ci :
VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
Expand Down Expand Up @@ -524,15 +524,15 @@ class VOP1_DPPe <bits<8> op, VOP1_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :
}

multiclass VOP1Only_Real_vi <bits<10> op> {
let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in {
def _vi :
VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.VI>,
VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>;
}
}

multiclass VOP1_Real_e32e64_vi <bits<10> op> {
let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in {
def _e32_vi :
VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
Expand Down Expand Up @@ -649,7 +649,7 @@ def V_MOV_B32_indirect : VPseudoInstSI<(outs),
PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,
getVOPSrc0ForVT<i32>.ret:$src0)> {
let VOP1 = 1;
let SubtargetPredicate = isVI;
let SubtargetPredicate = isGFX8GFX9;
}

// This is a pseudo variant of the v_movreld_b32 instruction in which the
Expand All @@ -672,7 +672,7 @@ def V_MOVRELD_B32_V4 : V_MOVRELD_B32_pseudo<VReg_128>;
def V_MOVRELD_B32_V8 : V_MOVRELD_B32_pseudo<VReg_256>;
def V_MOVRELD_B32_V16 : V_MOVRELD_B32_pseudo<VReg_512>;

let OtherPredicates = [isVI] in {
let OtherPredicates = [isGFX8GFX9] in {

def : GCNPat <
(i32 (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask,
Expand All @@ -690,7 +690,7 @@ def : GCNPat <
(as_i1imm $bound_ctrl))
>;

} // End OtherPredicates = [isVI]
} // End OtherPredicates = [isGFX8GFX9]

let OtherPredicates = [isGFX8Plus] in {
def : GCNPat<
Expand Down Expand Up @@ -722,7 +722,7 @@ def : GCNPat <
//===----------------------------------------------------------------------===//

multiclass VOP1_Real_gfx9 <bits<10> op> {
let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in {
let AssemblerPredicates = [isGFX9Only], DecoderNamespace = "GFX9" in {
defm NAME : VOP1_Real_e32e64_vi <op>;
}

Expand Down

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