PR25754: avoid generating UDIVREM8_ZEXT_HREG nodes with i64 result

Reviewers: spatel, srking

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D15331

llvm-svn: 256924

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -27419,7 +27419,7 @@ static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
   // from AH (which we otherwise need to do contortions to access).
   if (N0.getOpcode() == ISD::UDIVREM &&
       N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
-      (VT == MVT::i32 || VT == MVT::i64)) {
+      VT == MVT::i32) {
     SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
     SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
                             N0.getOperand(0), N0.getOperand(1));
@@ -27923,6 +27923,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
   case X86ISD::FANDN:       return PerformFANDNCombine(N, DAG, Subtarget);
   case X86ISD::BT:          return PerformBTCombine(N, DAG, DCI);
   case X86ISD::VZEXT_MOVL:  return PerformVZEXT_MOVLCombine(N, DAG);
+// TODO: refactor the [SU]DIVREM8_[SZ]EXT_HREG code so that it's not duplicated.
   case ISD::ANY_EXTEND:
   case ISD::ZERO_EXTEND:    return PerformZExtCombine(N, DAG, DCI, Subtarget);
   case ISD::SIGN_EXTEND:    return PerformSExtCombine(N, DAG, DCI, Subtarget);

llvm/test/CodeGen/X86/divrem8_ext.ll

@@ -97,4 +97,23 @@ define i64 @test_srem_sext64_ah(i8 %x, i8 %y) {
   ret i64 %2
 }
 
+define i64 @pr25754(i8 %a, i8 %c) {
+; CHECK-LABEL: pr25754
+; CHECK:    movzbl {{.+}}, %eax
+; CHECK:    divb
+; CHECK:    movzbl %ah, %ecx
+; CHECK:    movzbl %al, %eax
+; CHECK-32: addl %ecx, %eax
+; CHECK-32: sbbl %edx, %edx
+; CHECK-32: andl $1, %edx
+; CHECK-64: addq %rcx, %rax
+; CHECK:    ret
+  %r1 = urem i8 %a, %c
+  %d1 = udiv i8 %a, %c
+  %r2 = zext i8 %r1 to i64
+  %d2 = zext i8 %d1 to i64
+  %ret = add i64 %r2, %d2
+  ret i64 %ret
+}
+
 @z = external global i8