Skip to content

Commit

Permalink
revert r367382 because buildbot failure
Browse files Browse the repository at this point in the history 
llvm-svn: 367388
  • Loading branch information
@wuzish
wuzish committed Jul 31, 2019
1 parent 3be25e7 commit 54d446f
Show file tree
Hide file tree
Showing 6 changed files with 169 additions and 169 deletions.
71 changes: 0 additions & 71 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View file
Expand Up @@ -1118,8 +1118,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setTargetDAGCombine(ISD::ANY_EXTEND);

setTargetDAGCombine(ISD::TRUNCATE);
setTargetDAGCombine(ISD::VECTOR_SHUFFLE);


if (Subtarget.useCRBits()) {
setTargetDAGCombine(ISD::TRUNCATE);
Expand Down Expand Up @@ -1354,8 +1352,6 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
case PPCISD::SExtVElems: return "PPCISD::SExtVElems";
case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE";
case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE";
case PPCISD::ST_VSR_SCAL_INT:
return "PPCISD::ST_VSR_SCAL_INT";
case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
Expand Down Expand Up @@ -13117,60 +13113,6 @@ SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N,
return Val;
}

SDValue PPCTargetLowering::combineVReverseMemOP(ShuffleVectorSDNode *SVN,
LSBaseSDNode *LSBase,
DAGCombinerInfo &DCI) const {
assert((ISD::isNormalLoad(LSBase) || ISD::isNormalStore(LSBase)) &&
"Not a reverse memop pattern!");

auto IsElementReverse = [](const ShuffleVectorSDNode *SVN) -> bool {
auto Mask = SVN->getMask();
int i = 0;
auto I = Mask.rbegin();
auto E = Mask.rend();

for (; I != E; ++I) {
if (*I != i)
return false;
i++;
}
return true;
};

SelectionDAG &DAG = DCI.DAG;
EVT VT = SVN->getValueType(0);

if (!isTypeLegal(VT) || !Subtarget.isLittleEndian() || !Subtarget.hasVSX())
return SDValue();

// Before P9, we don't have vector load/store instrs in big-endian
// element order for v8i16 or v16i8
if (!Subtarget.hasP9Vector() && (VT == MVT::v8i16 || VT == MVT::v16i8))
return SDValue();

if(!IsElementReverse(SVN))
return SDValue();

if (LSBase->getOpcode() == ISD::LOAD) {
SDLoc dl(SVN);
SDValue LoadOps[] = {LSBase->getChain(), LSBase->getBasePtr()};
return DAG.getMemIntrinsicNode(
PPCISD::LOAD_VEC_BE, dl, DAG.getVTList(VT, MVT::Other), LoadOps,
LSBase->getMemoryVT(), LSBase->getMemOperand());
}

if (LSBase->getOpcode() == ISD::STORE) {
SDLoc dl(LSBase);
SDValue StoreOps[] = {LSBase->getChain(), SVN->getOperand(0),
LSBase->getBasePtr()};
return DAG.getMemIntrinsicNode(
PPCISD::STORE_VEC_BE, dl, DAG.getVTList(MVT::Other), StoreOps,
LSBase->getMemoryVT(), LSBase->getMemOperand());
}

llvm_unreachable("Expected a load or store node here");
}

SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
Expand Down Expand Up @@ -13217,12 +13159,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
return combineFPToIntToFP(N, DCI);
case ISD::VECTOR_SHUFFLE:
if (ISD::isNormalLoad(N->getOperand(0).getNode())) {
LSBaseSDNode* LSBase = cast<LSBaseSDNode>(N->getOperand(0));
return combineVReverseMemOP(cast<ShuffleVectorSDNode>(N), LSBase, DCI);
}
break;
case ISD::STORE: {

EVT Op1VT = N->getOperand(1).getValueType();
Expand All @@ -13234,13 +13170,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
return Val;
}

if (Opcode == ISD::VECTOR_SHUFFLE && ISD::isNormalStore(N)) {
ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N->getOperand(1));
SDValue Val= combineVReverseMemOP(SVN, cast<LSBaseSDNode>(N), DCI);
if (Val)
return Val;
}

// Turn STORE (BSWAP) -> sthbrx/stwbrx.
if (cast<StoreSDNode>(N)->isUnindexed() && Opcode == ISD::BSWAP &&
N->getOperand(1).getNode()->hasOneUse() &&
Expand Down
12 changes: 0 additions & 12 deletions llvm/lib/Target/PowerPC/PPCISelLowering.h
View file
Expand Up @@ -456,11 +456,6 @@ namespace llvm {
/// an xxswapd.
LXVD2X,

/// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
/// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on
/// the vector type to load vector in big-endian element order.
LOAD_VEC_BE,

/// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a
/// v2f32 value into the lower half of a VSR register.
LD_VSX_LH,
Expand All @@ -470,11 +465,6 @@ namespace llvm {
/// an xxswapd.
STXVD2X,

/// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
/// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on
/// the vector type to store vector in big-endian element order.
STORE_VEC_BE,

/// Store scalar integers from VSR.
ST_VSR_SCAL_INT,

Expand Down Expand Up @@ -1177,8 +1167,6 @@ namespace llvm {
SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase,
DAGCombinerInfo &DCI) const;

/// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
/// SETCC with integer subtraction when (1) there is a legal way of doing it
Expand Down
34 changes: 1 addition & 33 deletions llvm/lib/Target/PowerPC/PPCInstrVSX.td
View file
Expand Up @@ -78,21 +78,12 @@ def SDTVecConv : SDTypeProfile<1, 2, [
def SDTVabsd : SDTypeProfile<1, 3, [
SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<3, i32>
]>;
def SDT_PPCld_vec_be : SDTypeProfile<1, 1, [
SDTCisVec<0>, SDTCisPtrTy<1>
]>;
def SDT_PPCst_vec_be : SDTypeProfile<0, 2, [
SDTCisVec<0>, SDTCisPtrTy<1>
]>;


def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x,
[SDNPHasChain, SDNPMayStore]>;
def PPCld_vec_be : SDNode<"PPCISD::LOAD_VEC_BE", SDT_PPCld_vec_be,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def PPCst_vec_be : SDNode<"PPCISD::STORE_VEC_BE", SDT_PPCst_vec_be,
[SDNPHasChain, SDNPMayStore]>;
def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>;
def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
def PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>;
Expand Down Expand Up @@ -1097,19 +1088,6 @@ let Predicates = [HasVSX, HasOnlySwappingMemOps] in {
(STXVD2X $rS, xoaddr:$dst)>;
def : Pat<(PPCstxvd2x v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
}

// Load vector big endian order
let Predicates = [IsLittleEndian, HasVSX] in {
def : Pat<(v2f64 (PPCld_vec_be xoaddr:$src)), (LXVD2X xoaddr:$src)>;
def : Pat<(PPCst_vec_be v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
def : Pat<(v4f32 (PPCld_vec_be xoaddr:$src)), (LXVW4X xoaddr:$src)>;
def : Pat<(PPCst_vec_be v4f32:$rS, xoaddr:$dst), (STXVW4X $rS, xoaddr:$dst)>;
def : Pat<(v2i64 (PPCld_vec_be xoaddr:$src)), (LXVD2X xoaddr:$src)>;
def : Pat<(PPCst_vec_be v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
def : Pat<(v4i32 (PPCld_vec_be xoaddr:$src)), (LXVW4X xoaddr:$src)>;
def : Pat<(PPCst_vec_be v4i32:$rS, xoaddr:$dst), (STXVW4X $rS, xoaddr:$dst)>;
}

let Predicates = [IsBigEndian, HasVSX, HasOnlySwappingMemOps] in {
def : Pat<(v2f64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
def : Pat<(v2i64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
Expand Down Expand Up @@ -3046,16 +3024,6 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
(v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>;
def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)),
(v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>;

def : Pat<(v8i16 (PPCld_vec_be xoaddr:$src)),
(COPY_TO_REGCLASS (LXVH8X xoaddr:$src), VRRC)>;
def : Pat<(PPCst_vec_be v8i16:$rS, xoaddr:$dst),
(STXVH8X (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$dst)>;

def : Pat<(v16i8 (PPCld_vec_be xoaddr:$src)),
(COPY_TO_REGCLASS (LXVB16X xoaddr:$src), VRRC)>;
def : Pat<(PPCst_vec_be v16i8:$rS, xoaddr:$dst),
(STXVB16X (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$dst)>;
} // IsLittleEndian, HasP9Vector

let Predicates = [IsBigEndian, HasP9Vector] in {
Expand Down
62 changes: 42 additions & 20 deletions llvm/test/CodeGen/PowerPC/build-vector-tests.ll
View file
Expand Up @@ -986,7 +986,11 @@ define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) {
;
; P9LE-LABEL: fromDiffMemConsDi:
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lxvw4x v2, 0, r3
; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: addis r3, r2, .LCPI8_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI8_0@toc@l
; P9LE-NEXT: lxvx v3, 0, r3
; P9LE-NEXT: vperm v2, v2, v2, v3
; P9LE-NEXT: blr
;
; P8BE-LABEL: fromDiffMemConsDi:
Expand All @@ -1000,7 +1004,12 @@ define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) {
;
; P8LE-LABEL: fromDiffMemConsDi:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lxvw4x v2, 0, r3
; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: addis r4, r2, .LCPI8_0@toc@ha
; P8LE-NEXT: addi r3, r4, .LCPI8_0@toc@l
; P8LE-NEXT: lvx v2, 0, r3
; P8LE-NEXT: xxswapd v3, vs0
; P8LE-NEXT: vperm v2, v3, v3, v2
; P8LE-NEXT: blr
entry:
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 3
Expand Down Expand Up @@ -2561,7 +2570,11 @@ define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) {
;
; P9LE-LABEL: fromDiffMemConsDui:
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lxvw4x v2, 0, r3
; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l
; P9LE-NEXT: lxvx v3, 0, r3
; P9LE-NEXT: vperm v2, v2, v2, v3
; P9LE-NEXT: blr
;
; P8BE-LABEL: fromDiffMemConsDui:
Expand All @@ -2575,7 +2588,12 @@ define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) {
;
; P8LE-LABEL: fromDiffMemConsDui:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lxvw4x v2, 0, r3
; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: addis r4, r2, .LCPI41_0@toc@ha
; P8LE-NEXT: addi r3, r4, .LCPI41_0@toc@l
; P8LE-NEXT: lvx v2, 0, r3
; P8LE-NEXT: xxswapd v3, vs0
; P8LE-NEXT: vperm v2, v3, v3, v2
; P8LE-NEXT: blr
entry:
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 3
Expand Down Expand Up @@ -4137,8 +4155,8 @@ define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) {
;
; P9LE-LABEL: fromDiffMemConsDll:
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addi r3, r3, 16
; P9LE-NEXT: lxvd2x v2, 0, r3
; P9LE-NEXT: lxv v2, 16(r3)
; P9LE-NEXT: xxswapd v2, v2
; P9LE-NEXT: blr
;
; P8BE-LABEL: fromDiffMemConsDll:
Expand Down Expand Up @@ -4217,8 +4235,9 @@ define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %e
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r4, 3
; P9LE-NEXT: add r3, r3, r4
; P9LE-NEXT: addi r3, r3, -8
; P9LE-NEXT: lxvd2x v2, 0, r3
; P9LE-NEXT: li r4, -8
; P9LE-NEXT: lxvx v2, r3, r4
; P9LE-NEXT: xxswapd v2, v2
; P9LE-NEXT: blr
;
; P8BE-LABEL: fromDiffMemVarDll:
Expand Down Expand Up @@ -4929,8 +4948,8 @@ define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) {
;
; P9LE-LABEL: fromDiffMemConsDConvdtoll:
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addi r3, r3, 16
; P9LE-NEXT: lxvd2x vs0, 0, r3
; P9LE-NEXT: lxv vs0, 16(r3)
; P9LE-NEXT: xxswapd vs0, vs0
; P9LE-NEXT: xvcvdpsxds v2, vs0
; P9LE-NEXT: blr
;
Expand Down Expand Up @@ -5021,8 +5040,9 @@ define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r4, 3
; P9LE-NEXT: add r3, r3, r4
; P9LE-NEXT: addi r3, r3, -8
; P9LE-NEXT: lxvd2x vs0, 0, r3
; P9LE-NEXT: li r4, -8
; P9LE-NEXT: lxvx vs0, r3, r4
; P9LE-NEXT: xxswapd vs0, vs0
; P9LE-NEXT: xvcvdpsxds v2, vs0
; P9LE-NEXT: blr
;
Expand Down Expand Up @@ -5382,8 +5402,8 @@ define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) {
;
; P9LE-LABEL: fromDiffMemConsDull:
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addi r3, r3, 16
; P9LE-NEXT: lxvd2x v2, 0, r3
; P9LE-NEXT: lxv v2, 16(r3)
; P9LE-NEXT: xxswapd v2, v2
; P9LE-NEXT: blr
;
; P8BE-LABEL: fromDiffMemConsDull:
Expand Down Expand Up @@ -5462,8 +5482,9 @@ define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r4, 3
; P9LE-NEXT: add r3, r3, r4
; P9LE-NEXT: addi r3, r3, -8
; P9LE-NEXT: lxvd2x v2, 0, r3
; P9LE-NEXT: li r4, -8
; P9LE-NEXT: lxvx v2, r3, r4
; P9LE-NEXT: xxswapd v2, v2
; P9LE-NEXT: blr
;
; P8BE-LABEL: fromDiffMemVarDull:
Expand Down Expand Up @@ -6174,8 +6195,8 @@ define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) {
;
; P9LE-LABEL: fromDiffMemConsDConvdtoull:
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addi r3, r3, 16
; P9LE-NEXT: lxvd2x vs0, 0, r3
; P9LE-NEXT: lxv vs0, 16(r3)
; P9LE-NEXT: xxswapd vs0, vs0
; P9LE-NEXT: xvcvdpuxds v2, vs0
; P9LE-NEXT: blr
;
Expand Down Expand Up @@ -6266,8 +6287,9 @@ define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r4, 3
; P9LE-NEXT: add r3, r3, r4
; P9LE-NEXT: addi r3, r3, -8
; P9LE-NEXT: lxvd2x vs0, 0, r3
; P9LE-NEXT: li r4, -8
; P9LE-NEXT: lxvx vs0, r3, r4
; P9LE-NEXT: xxswapd vs0, vs0
; P9LE-NEXT: xvcvdpuxds v2, vs0
; P9LE-NEXT: blr
;
Expand Down

0 comments on commit 54d446f

Please sign in to comment.