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[RISCV] Disable lax vector conversions between RVVBuiltin types and R…
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…VVFixedLengthDataVector.

This seems to be causing issues with using overloaded RVV intrinsics
that take scalar operands. If the scalar type passed in doesn't exactly
match the element type.

I blindly copied this feature from SVE. Since no one has asked for it
I'd prefer to remove it to make overloaded intrinsics work as expected.

By removing the lax conversions, types declared with __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)))
can only ever be used like their underlying RVV builtin type. No lax conversions
to other element sizes with the same LMUL.

Fixes #64404.
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@topperc
topperc committed Oct 26, 2023
1 parent e39f6c1 commit 56183cf
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Showing 4 changed files with 20 additions and 24 deletions.
4 changes: 1 addition & 3 deletions clang/lib/AST/ASTContext.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9563,9 +9563,7 @@ bool ASTContext::areLaxCompatibleRVVTypes(QualType FirstType,
return false;

const auto *VecTy = SecondType->getAs<VectorType>();
if (VecTy &&
(VecTy->getVectorKind() == VectorType::RVVFixedLengthDataVector ||
VecTy->getVectorKind() == VectorType::GenericVector)) {
if (VecTy && VecTy->getVectorKind() == VectorType::GenericVector) {
const LangOptions::LaxVectorConversionKind LVCKind =
getLangOpts().getLaxVectorConversions();

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26 changes: 7 additions & 19 deletions clang/test/CodeGen/attr-riscv-rvv-vector-bits-cast.c
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Original file line number Diff line number Diff line change
Expand Up @@ -55,32 +55,20 @@ fixed_float64m1_t from_vfloat64m1_t(vfloat64m1_t type) {
return type;
}

// CHECK-LABEL: @lax_cast(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[SAVED_VALUE:%.*]] = alloca <8 x i32>, align 32
// CHECK-NEXT: [[TYPE:%.*]] = tail call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> [[TYPE_COERCE:%.*]], i64 0)
// CHECK-NEXT: store <8 x i32> [[TYPE]], ptr [[SAVED_VALUE]], align 32, !tbaa [[TBAA4:![0-9]+]]
// CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 1 x i64>, ptr [[SAVED_VALUE]], align 32, !tbaa [[TBAA4]]
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t lax_cast(fixed_int32m1_t type) {
return type;
}

// CHECK-LABEL: @to_vint32m1_t__from_gnu_int32m1_t(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TYPE:%.*]] = load <8 x i32>, ptr [[TMP0:%.*]], align 32, !tbaa [[TBAA4]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = tail call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> undef, <8 x i32> [[TYPE]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i32> [[CASTSCALABLESVE]]
// CHECK-NEXT: [[TYPE:%.*]] = load <8 x i32>, ptr [[TMP0:%.*]], align 32, !tbaa [[TBAA4:![0-9]+]]
// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = tail call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> undef, <8 x i32> [[TYPE]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i32> [[CAST_SCALABLE]]
//
vint32m1_t to_vint32m1_t__from_gnu_int32m1_t(gnu_int32m1_t type) {
return type;
}

// CHECK-LABEL: @from_vint32m1_t__to_gnu_int32m1_t(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = tail call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> [[TYPE:%.*]], i64 0)
// CHECK-NEXT: store <8 x i32> [[CASTFIXEDSVE]], ptr [[AGG_RESULT:%.*]], align 32, !tbaa [[TBAA4]]
// CHECK-NEXT: [[CAST_FIXED:%.*]] = tail call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> [[TYPE:%.*]], i64 0)
// CHECK-NEXT: store <8 x i32> [[CAST_FIXED]], ptr [[AGG_RESULT:%.*]], align 32, !tbaa [[TBAA4]]
// CHECK-NEXT: ret void
//
gnu_int32m1_t from_vint32m1_t__to_gnu_int32m1_t(vint32m1_t type) {
Expand All @@ -90,8 +78,8 @@ gnu_int32m1_t from_vint32m1_t__to_gnu_int32m1_t(vint32m1_t type) {
// CHECK-LABEL: @to_fixed_int32m1_t__from_gnu_int32m1_t(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TYPE:%.*]] = load <8 x i32>, ptr [[TMP0:%.*]], align 32, !tbaa [[TBAA4]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = tail call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> undef, <8 x i32> [[TYPE]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i32> [[CASTSCALABLESVE]]
// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = tail call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> undef, <8 x i32> [[TYPE]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i32> [[CAST_SCALABLE]]
//
fixed_int32m1_t to_fixed_int32m1_t__from_gnu_int32m1_t(gnu_int32m1_t type) {
return type;
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6 changes: 6 additions & 0 deletions clang/test/Sema/riscv-rvv-lax-vector-conversions.c
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Original file line number Diff line number Diff line change
Expand Up @@ -33,8 +33,12 @@ void rvv_allowed_with_integer_lax_conversions() {
// -flax-vector-conversions={integer,all}.
fi32 = si64;
// lax-vector-none-error@-1 {{assigning to 'rvv_fixed_int32m1_t' (vector of 16 'int' values) from incompatible type}}
// lax-vector-integer-error@-2 {{assigning to 'rvv_fixed_int32m1_t' (vector of 16 'int' values) from incompatible type}}
// lax-vector-all-error@-3 {{assigning to 'rvv_fixed_int32m1_t' (vector of 16 'int' values) from incompatible type}}
si64 = fi32;
// lax-vector-none-error@-1 {{assigning to 'vint64m1_t' (aka '__rvv_int64m1_t') from incompatible type}}
// lax-vector-integer-error@-2 {{assigning to 'vint64m1_t' (aka '__rvv_int64m1_t') from incompatible type}}
// lax-vector-all-error@-3 {{assigning to 'vint64m1_t' (aka '__rvv_int64m1_t') from incompatible type}}
}

void rvv_allowed_with_all_lax_conversions() {
Expand All @@ -46,9 +50,11 @@ void rvv_allowed_with_all_lax_conversions() {
ff32 = sf64;
// lax-vector-none-error@-1 {{assigning to 'rvv_fixed_float32m1_t' (vector of 16 'float' values) from incompatible type}}
// lax-vector-integer-error@-2 {{assigning to 'rvv_fixed_float32m1_t' (vector of 16 'float' values) from incompatible type}}
// lax-vector-all-error@-3 {{assigning to 'rvv_fixed_float32m1_t' (vector of 16 'float' values) from incompatible type}}
sf64 = ff32;
// lax-vector-none-error@-1 {{assigning to 'vfloat64m1_t' (aka '__rvv_float64m1_t') from incompatible type}}
// lax-vector-integer-error@-2 {{assigning to 'vfloat64m1_t' (aka '__rvv_float64m1_t') from incompatible type}}
// lax-vector-all-error@-3 {{assigning to 'vfloat64m1_t' (aka '__rvv_float64m1_t') from incompatible type}}
}

void gnu_allowed_with_integer_lax_conversions() {
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8 changes: 6 additions & 2 deletions clang/test/SemaCXX/riscv-rvv-lax-vector-conversions.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,6 @@
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 -flax-vector-conversions=integer -ffreestanding -fsyntax-only -verify=lax-vector-integer %s
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 -flax-vector-conversions=all -ffreestanding -fsyntax-only -verify=lax-vector-all %s

// lax-vector-all-no-diagnostics

// REQUIRES: riscv-registered-target

#define RVV_FIXED_ATTR __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)))
Expand Down Expand Up @@ -33,8 +31,12 @@ void rvv_allowed_with_integer_lax_conversions() {
// -flax-vector-conversions={integer,all}.
fi32 = si64;
// lax-vector-none-error@-1 {{assigning to 'rvv_fixed_int32m1_t' (vector of 16 'int' values) from incompatible type}}
// lax-vector-integer-error@-2 {{assigning to 'rvv_fixed_int32m1_t' (vector of 16 'int' values) from incompatible type}}
// lax-vector-all-error@-3 {{assigning to 'rvv_fixed_int32m1_t' (vector of 16 'int' values) from incompatible type}}
si64 = fi32;
// lax-vector-none-error@-1 {{assigning to 'vint64m1_t' (aka '__rvv_int64m1_t') from incompatible type}}
// lax-vector-integer-error@-2 {{assigning to 'vint64m1_t' (aka '__rvv_int64m1_t') from incompatible type}}
// lax-vector-all-error@-3 {{assigning to 'vint64m1_t' (aka '__rvv_int64m1_t') from incompatible type}}
}

void rvv_allowed_with_all_lax_conversions() {
Expand All @@ -46,9 +48,11 @@ void rvv_allowed_with_all_lax_conversions() {
ff32 = sf64;
// lax-vector-none-error@-1 {{assigning to 'rvv_fixed_float32m1_t' (vector of 16 'float' values) from incompatible type}}
// lax-vector-integer-error@-2 {{assigning to 'rvv_fixed_float32m1_t' (vector of 16 'float' values) from incompatible type}}
// lax-vector-all-error@-3 {{assigning to 'rvv_fixed_float32m1_t' (vector of 16 'float' values) from incompatible type}}
sf64 = ff32;
// lax-vector-none-error@-1 {{assigning to 'vfloat64m1_t' (aka '__rvv_float64m1_t') from incompatible type}}
// lax-vector-integer-error@-2 {{assigning to 'vfloat64m1_t' (aka '__rvv_float64m1_t') from incompatible type}}
// lax-vector-all-error@-3 {{assigning to 'vfloat64m1_t' (aka '__rvv_float64m1_t') from incompatible type}}
}

void gnu_allowed_with_integer_lax_conversions() {
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