[SLP][NFC]Add a test for vectorization with scheduling blocks order

different than the instruction order, NFC.

llvm/test/Transforms/SLPVectorizer/X86/slp-schedule-use-order.ll

@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+define void @test() {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi <2 x i1> [ [[TMP8:%.*]], [[TMP1:%.*]] ], [ zeroinitializer, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    br label [[TMP1]]
+; CHECK:       1:
+; CHECK-NEXT:    [[TMP2:%.*]] = zext <2 x i1> [[TMP0]] to <2 x i8>
+; CHECK-NEXT:    [[TMP3:%.*]] = or i8 0, 0
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i8> <i8 poison, i8 0>, i8 [[TMP3]], i32 0
+; CHECK-NEXT:    [[TMP5:%.*]] = and <2 x i8> [[TMP4]], [[TMP2]]
+; CHECK-NEXT:    [[TMP6:%.*]] = or <2 x i8> [[TMP5]], zeroinitializer
+; CHECK-NEXT:    [[TMP7:%.*]] = icmp ne <2 x i8> [[TMP6]], zeroinitializer
+; CHECK-NEXT:    [[TMP8]] = and <2 x i1> [[TMP7]], zeroinitializer
+; CHECK-NEXT:    br label [[FOR_BODY]]
+;
+entry:
+  br label %for.body
+
+for.body:
+  %phi1 = phi i1 [ %icmp2, %0 ], [ false, %entry ]
+  %phi2 = phi i1 [ %icmp1, %0 ], [ false, %entry ]
+  br label %0
+
+0:
+  %z1 = zext i1 %phi2 to i8
+  %1 = and i8 0, %z1
+  %2 = and i8 0, 0
+  %3 = or i8 %1, %2
+  %4 = icmp ne i8 %3, 0
+  %icmp1 = and i1 %4, false
+  %5 = or i8 0, 0
+  %z2 = zext i1 %phi1 to i8
+  %6 = and i8 %5, %z2
+  %7 = and i8 0, 0
+  %8 = or i8 %6, %7
+  %9 = icmp ne i8 %8, 0
+  %icmp2 = and i1 %9, false
+  br label %for.body
+}