[RISCV][GISel] Test G_FRAME_INDEX folding into store address. NFC

llvm · Nov 25, 2023 · 564ff80 · 564ff80
1 parent bc6b632
commit 564ff80
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diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
@@ -1,6 +1,17 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
 # RUN: | FileCheck %s
+#
+--- |
+  define void @store_i8(i8 %val, ptr %addr) { ret void }
+  define void @store_i16(i16 %val, ptr %addr) { ret void }
+  define void @store_i32(i32 %val, ptr %addr) { ret void }
+  define void @store_p0(ptr %val, ptr %addr) { ret void }
+  define void @store_fi_i32(ptr %val) {
+    %ptr0 = alloca i32
+    ret void
+  }
+...
 ---
 name:            store_i8
 legalized:       true
@@ -89,3 +100,28 @@ body:            |
     PseudoRET
 
 ...
+---
+name:            store_fi_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+stack:
+  - { id: 0, name: ptr0, offset: 0, size: 4, alignment: 4 }
+
+body:            |
+  bb.0:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: store_fi_i32
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: SW [[COPY]], %stack.0.ptr0, 0 :: (store (s32))
+    ; CHECK-NEXT: PseudoRET
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
+    G_STORE %0(s32), %1(p0) :: (store (s32))
+    PseudoRET
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
@@ -1,6 +1,21 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
 # RUN: | FileCheck %s
+
+--- |
+  define void @store_i8_i64(i8 %val, ptr %addr) { ret void }
+  define void @store_i16_i64(i16 %val, ptr %addr) { ret void }
+  define void @store_i32_i64(i32 %val, ptr %addr) { ret void }
+  define void @store_i64_i64(i32 %val, ptr %addr) { ret void }
+  define void @store_p0(ptr %val, ptr %addr) { ret void }
+  define void @truncstore_i8_i32(i8 %val, ptr %addr) { ret void }
+  define void @truncstore_i16_i32(i8 %val, ptr %addr) { ret void }
+  define void @store_i32_i32(i8 %val, ptr %addr) { ret void }
+  define void @store_fi_i64_i64(ptr %val) {
+    %ptr0 = alloca i64
+    ret void
+  }
+...
 ---
 name:            store_i8_i64
 legalized:       true
@@ -207,3 +222,28 @@ body:             |
     PseudoRET implicit $x10
 
 ...
+---
+name:            store_fi_i64_i64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+stack:
+  - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
+
+body:            |
+  bb.0:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: store_fi_i64_i64
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: SD [[COPY]], %stack.0.ptr0, 0 :: (store (s64))
+    ; CHECK-NEXT: PseudoRET
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
+    G_STORE %0(s64), %1(p0) :: (store (s64))
+    PseudoRET
+
+...