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[X86] Enable 8-bit OR with disjoint bits to convert to LEA
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We already support 8-bits adds in convertToThreeAddress. But we can also support 8-bit OR if the bits are disjoint. We already do this for 16/32/64.

Differential Revision: https://reviews.llvm.org/D58863

llvm-svn: 355423
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@topperc
topperc committed Mar 5, 2019
1 parent bb322e7 commit 572e94c
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Showing 16 changed files with 146 additions and 103 deletions.
7 changes: 7 additions & 0 deletions llvm/lib/Target/X86/X86InstrCompiler.td
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Expand Up @@ -1381,6 +1381,9 @@ let SchedRW = [WriteALU] in {
let isConvertibleToThreeAddress = 1,
Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
let isCommutable = 1 in {
def ADD8rr_DB : I<0, Pseudo, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"", // orb/addb REG, REG
[(set GR8:$dst, (or_is_add GR8:$src1, GR8:$src2))]>;
def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"", // orw/addw REG, REG
[(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
Expand All @@ -1395,6 +1398,10 @@ def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
// NOTE: These are order specific, we want the ri8 forms to be listed
// first so that they are slightly preferred to the ri forms.

def ADD8ri_DB : I<0, Pseudo,
(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
"", // orb/addb REG, imm8
[(set GR8:$dst, (or_is_add GR8:$src1, imm:$src2))]>;
def ADD16ri8_DB : I<0, Pseudo,
(outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
"", // orw/addw REG, imm8
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/X86/X86InstrFoldTables.cpp
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Expand Up @@ -65,7 +65,9 @@ static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
{ X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
{ X86::ADD8ri, X86::ADD8mi, 0 },
{ X86::ADD8ri8, X86::ADD8mi8, 0 },
{ X86::ADD8ri_DB, X86::ADD8mi, TB_NO_REVERSE },
{ X86::ADD8rr, X86::ADD8mr, 0 },
{ X86::ADD8rr_DB, X86::ADD8mr, TB_NO_REVERSE },
{ X86::AND16ri, X86::AND16mi, 0 },
{ X86::AND16ri8, X86::AND16mi8, 0 },
{ X86::AND16rr, X86::AND16mr, 0 },
Expand Down Expand Up @@ -1218,6 +1220,7 @@ static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
{ X86::ADD64rr, X86::ADD64rm, 0 },
{ X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
{ X86::ADD8rr, X86::ADD8rm, 0 },
{ X86::ADD8rr_DB, X86::ADD8rm, TB_NO_REVERSE },
{ X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
{ X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
{ X86::ADDSDrr, X86::ADDSDrm, 0 },
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26 changes: 17 additions & 9 deletions llvm/lib/Target/X86/X86InstrInfo.cpp
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Expand Up @@ -710,11 +710,10 @@ bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,

MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
LiveVariables *LV) const {
LiveVariables *LV, bool Is8BitOp) const {
// We handle 8-bit adds and various 16-bit opcodes in the switch below.
bool Is16BitOp = !(MIOpc == X86::ADD8rr || MIOpc == X86::ADD8ri);
MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
assert((!Is16BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
*RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
"Unexpected type for LEA transform");

Expand Down Expand Up @@ -744,7 +743,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
unsigned Src = MI.getOperand(1).getReg();
bool IsDead = MI.getOperand(0).isDead();
bool IsKill = MI.getOperand(1).isKill();
unsigned SubReg = Is16BitOp ? X86::sub_16bit : X86::sub_8bit;
unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
MachineInstr *InsMI =
Expand All @@ -769,13 +768,15 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
addRegOffset(MIB, InRegLEA, true, -1);
break;
case X86::ADD8ri:
case X86::ADD8ri_DB:
case X86::ADD16ri:
case X86::ADD16ri8:
case X86::ADD16ri_DB:
case X86::ADD16ri8_DB:
addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
break;
case X86::ADD8rr:
case X86::ADD8rr_DB:
case X86::ADD16rr:
case X86::ADD16rr_DB: {
unsigned Src2 = MI.getOperand(2).getReg();
Expand Down Expand Up @@ -862,6 +863,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
MachineInstr *NewMI = nullptr;
bool Is64Bit = Subtarget.is64Bit();

bool Is8BitOp = false;
unsigned MIOpc = MI.getOpcode();
switch (MIOpc) {
default: return nullptr;
Expand Down Expand Up @@ -919,7 +921,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned ShAmt = getTruncatedShiftCount(MI, 2);
if (!isTruncatedShiftCountForLEA(ShAmt))
return nullptr;
return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
}
case X86::INC64r:
case X86::INC32r: {
Expand All @@ -944,7 +946,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
break;
}
case X86::INC16r:
return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
case X86::DEC64r:
case X86::DEC32r: {
assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
Expand All @@ -969,7 +971,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
break;
}
case X86::DEC16r:
return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
case X86::ADD64rr:
case X86::ADD64rr_DB:
case X86::ADD32rr:
Expand Down Expand Up @@ -1008,9 +1010,12 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
break;
}
case X86::ADD8rr:
case X86::ADD8rr_DB:
Is8BitOp = true;
LLVM_FALLTHROUGH;
case X86::ADD16rr:
case X86::ADD16rr_DB:
return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
case X86::ADD64ri32:
case X86::ADD64ri8:
case X86::ADD64ri32_DB:
Expand Down Expand Up @@ -1044,11 +1049,14 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
break;
}
case X86::ADD8ri:
case X86::ADD8ri_DB:
Is8BitOp = true;
LLVM_FALLTHROUGH;
case X86::ADD16ri:
case X86::ADD16ri8:
case X86::ADD16ri_DB:
case X86::ADD16ri8_DB:
return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
case X86::VMOVDQU8Z128rmk:
case X86::VMOVDQU8Z256rmk:
case X86::VMOVDQU8Zrmk:
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/X86/X86InstrInfo.h
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Expand Up @@ -592,7 +592,8 @@ class X86InstrInfo final : public X86GenInstrInfo {
MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
MachineFunction::iterator &MFI,
MachineInstr &MI,
LiveVariables *LV) const;
LiveVariables *LV,
bool Is8BitOp) const;

/// Handles memory folding for special case instructions, for instance those
/// requiring custom manipulation of the address.
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/X86/X86MCInstLower.cpp
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Expand Up @@ -586,9 +586,11 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
// These are pseudo-ops for OR to help with the OR->ADD transformation. We do
// this with an ugly goto in case the resultant OR uses EAX and needs the
// short form.
case X86::ADD8rr_DB: OutMI.setOpcode(X86::OR8rr); goto ReSimplify;
case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
case X86::ADD8ri_DB: OutMI.setOpcode(X86::OR8ri); goto ReSimplify;
case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/X86/X86MacroFusion.cpp
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Expand Up @@ -140,8 +140,10 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
case X86::ADD64rr:
case X86::ADD64rr_DB:
case X86::ADD8ri:
case X86::ADD8ri_DB:
case X86::ADD8rm:
case X86::ADD8rr:
case X86::ADD8rr_DB:
case X86::SUB16ri:
case X86::SUB16ri8:
case X86::SUB16rm:
Expand Down
52 changes: 26 additions & 26 deletions llvm/test/CodeGen/X86/bitreverse.ll
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Expand Up @@ -340,20 +340,20 @@ define i8 @test_bitreverse_i8(i8 %a) {
;
; X64-LABEL: test_bitreverse_i8:
; X64: # %bb.0:
; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: rolb $4, %dil
; X64-NEXT: movl %edi, %eax
; X64-NEXT: rolb $4, %al
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: andb $51, %cl
; X64-NEXT: shlb $2, %cl
; X64-NEXT: andb $-52, %al
; X64-NEXT: shrb $2, %al
; X64-NEXT: orb %cl, %al
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: andb $85, %cl
; X64-NEXT: addb %cl, %cl
; X64-NEXT: andb $-86, %al
; X64-NEXT: shrb %al
; X64-NEXT: orb %cl, %al
; X64-NEXT: andb $51, %al
; X64-NEXT: shlb $2, %al
; X64-NEXT: andb $-52, %dil
; X64-NEXT: shrb $2, %dil
; X64-NEXT: orb %al, %dil
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andb $85, %al
; X64-NEXT: addb %al, %al
; X64-NEXT: andb $-86, %dil
; X64-NEXT: shrb %dil
; X64-NEXT: leal (%rdi,%rax), %eax
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
%b = call i8 @llvm.bitreverse.i8(i8 %a)
Expand Down Expand Up @@ -384,20 +384,20 @@ define i4 @test_bitreverse_i4(i4 %a) {
;
; X64-LABEL: test_bitreverse_i4:
; X64: # %bb.0:
; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: rolb $4, %dil
; X64-NEXT: movl %edi, %eax
; X64-NEXT: rolb $4, %al
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: andb $51, %cl
; X64-NEXT: shlb $2, %cl
; X64-NEXT: andb $-52, %al
; X64-NEXT: shrb $2, %al
; X64-NEXT: orb %cl, %al
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: andb $80, %cl
; X64-NEXT: addb %cl, %cl
; X64-NEXT: andb $-96, %al
; X64-NEXT: shrb %al
; X64-NEXT: orb %cl, %al
; X64-NEXT: andb $51, %al
; X64-NEXT: shlb $2, %al
; X64-NEXT: andb $-52, %dil
; X64-NEXT: shrb $2, %dil
; X64-NEXT: orb %al, %dil
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andb $80, %al
; X64-NEXT: addb %al, %al
; X64-NEXT: andb $-96, %dil
; X64-NEXT: shrb %dil
; X64-NEXT: leal (%rdi,%rax), %eax
; X64-NEXT: shrb $4, %al
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/bool-math.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -47,9 +47,9 @@ define i32 @sub_zext_cmp_mask_wider_result(i8 %x) {
define i8 @sub_zext_cmp_mask_narrower_result(i32 %x) {
; X64-LABEL: sub_zext_cmp_mask_narrower_result:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andb $1, %al
; X64-NEXT: orb $46, %al
; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: andb $1, %dil
; X64-NEXT: leal 46(%rdi), %eax
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
;
Expand Down
7 changes: 4 additions & 3 deletions llvm/test/CodeGen/X86/fshl.ll
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Expand Up @@ -381,10 +381,11 @@ define i8 @const_shift_i8(i8 %x, i8 %y) nounwind {
;
; X64-LABEL: const_shift_i8:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: shrb %sil
; X64-NEXT: shlb $7, %al
; X64-NEXT: orb %sil, %al
; X64-NEXT: shlb $7, %dil
; X64-NEXT: leal (%rdi,%rsi), %eax
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
%tmp = tail call i8 @llvm.fshl.i8(i8 %x, i8 %y, i8 7)
Expand Down
27 changes: 19 additions & 8 deletions llvm/test/CodeGen/X86/select.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1088,14 +1088,25 @@ define i8 @test18(i32 %x, i8 zeroext %a, i8 zeroext %b) nounwind {
}

define i32 @trunc_select_miscompile(i32 %a, i1 zeroext %cc) {
; CHECK-LABEL: trunc_select_miscompile:
; CHECK: ## %bb.0:
; CHECK-NEXT: movl %esi, %ecx
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: orb $2, %cl
; CHECK-NEXT: ## kill: def $cl killed $cl killed $ecx
; CHECK-NEXT: shll %cl, %eax
; CHECK-NEXT: retq
; GENERIC-LABEL: trunc_select_miscompile:
; GENERIC: ## %bb.0:
; GENERIC-NEXT: ## kill: def $esi killed $esi def $rsi
; GENERIC-NEXT: movl %edi, %eax
; GENERIC-NEXT: leal 2(%rsi), %ecx
; GENERIC-NEXT: ## kill: def $cl killed $cl killed $ecx
; GENERIC-NEXT: shll %cl, %eax
; GENERIC-NEXT: retq
;
; ATOM-LABEL: trunc_select_miscompile:
; ATOM: ## %bb.0:
; ATOM-NEXT: ## kill: def $esi killed $esi def $rsi
; ATOM-NEXT: leal 2(%rsi), %ecx
; ATOM-NEXT: movl %edi, %eax
; ATOM-NEXT: ## kill: def $cl killed $cl killed $ecx
; ATOM-NEXT: shll %cl, %eax
; ATOM-NEXT: nop
; ATOM-NEXT: nop
; ATOM-NEXT: retq
;
; ATHLON-LABEL: trunc_select_miscompile:
; ATHLON: ## %bb.0:
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/select_const.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -328,9 +328,9 @@ define i32 @sel_neg1_1_32(i32 %x) {
define i8 @select_pow2_diff(i1 zeroext %cond) {
; CHECK-LABEL: select_pow2_diff:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: shlb $4, %al
; CHECK-NEXT: orb $3, %al
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-NEXT: shlb $4, %dil
; CHECK-NEXT: leal 3(%rdi), %eax
; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%sel = select i1 %cond, i8 19, i8 3
Expand Down
14 changes: 8 additions & 6 deletions llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-innerouter.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -10,19 +10,21 @@
define i8 @out8_constmask(i8 %x, i8 %y) {
; CHECK-NOBMI-LABEL: out8_constmask:
; CHECK-NOBMI: # %bb.0:
; CHECK-NOBMI-NEXT: movl %esi, %eax
; CHECK-NOBMI-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NOBMI-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-NOBMI-NEXT: andb $60, %dil
; CHECK-NOBMI-NEXT: andb $-61, %al
; CHECK-NOBMI-NEXT: orb %dil, %al
; CHECK-NOBMI-NEXT: andb $-61, %sil
; CHECK-NOBMI-NEXT: leal (%rsi,%rdi), %eax
; CHECK-NOBMI-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NOBMI-NEXT: retq
;
; CHECK-BMI-LABEL: out8_constmask:
; CHECK-BMI: # %bb.0:
; CHECK-BMI-NEXT: movl %esi, %eax
; CHECK-BMI-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-BMI-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-BMI-NEXT: andb $60, %dil
; CHECK-BMI-NEXT: andb $-61, %al
; CHECK-BMI-NEXT: orb %dil, %al
; CHECK-BMI-NEXT: andb $-61, %sil
; CHECK-BMI-NEXT: leal (%rsi,%rdi), %eax
; CHECK-BMI-NEXT: # kill: def $al killed $al killed $eax
; CHECK-BMI-NEXT: retq
%mx = and i8 %x, 60
Expand Down
14 changes: 8 additions & 6 deletions llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbits.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -10,19 +10,21 @@
define i8 @out8_constmask(i8 %x, i8 %y) {
; CHECK-NOBMI-LABEL: out8_constmask:
; CHECK-NOBMI: # %bb.0:
; CHECK-NOBMI-NEXT: movl %esi, %eax
; CHECK-NOBMI-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NOBMI-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-NOBMI-NEXT: andb $85, %dil
; CHECK-NOBMI-NEXT: andb $-86, %al
; CHECK-NOBMI-NEXT: orb %dil, %al
; CHECK-NOBMI-NEXT: andb $-86, %sil
; CHECK-NOBMI-NEXT: leal (%rsi,%rdi), %eax
; CHECK-NOBMI-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NOBMI-NEXT: retq
;
; CHECK-BMI-LABEL: out8_constmask:
; CHECK-BMI: # %bb.0:
; CHECK-BMI-NEXT: movl %esi, %eax
; CHECK-BMI-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-BMI-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-BMI-NEXT: andb $85, %dil
; CHECK-BMI-NEXT: andb $-86, %al
; CHECK-BMI-NEXT: orb %dil, %al
; CHECK-BMI-NEXT: andb $-86, %sil
; CHECK-BMI-NEXT: leal (%rsi,%rdi), %eax
; CHECK-BMI-NEXT: # kill: def $al killed $al killed $eax
; CHECK-BMI-NEXT: retq
%mx = and i8 %x, 85
Expand Down

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