[InstCombine] Add vector tests for icmp_eq(add(X,C1),add(Y,C2)) -> ic…

…mp_eq(add(X,C1-C2),Y) As mentioned on Issue #32161 we don't even have uniform vector support for this fold
llvm · Mar 10, 2022 · 5979c65 · 5979c65
1 parent 7f230fe
commit 5979c65
Showing 1 changed file with 78 additions and 0 deletions.
diff --git a/llvm/test/Transforms/InstCombine/icmp.ll b/llvm/test/Transforms/InstCombine/icmp.ll
@@ -1579,6 +1579,45 @@ define i1 @icmp_add20_sge_add57(i32 %x, i32 %y) {
   ret i1 %cmp
 }
 
+define <2 x i1> @icmp_add20_sge_add57_splat(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @icmp_add20_sge_add57_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = add nsw <2 x i32> [[X:%.*]], <i32 20, i32 20>
+; CHECK-NEXT:    [[TMP2:%.*]] = add nsw <2 x i32> [[Y:%.*]], <i32 57, i32 57>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sge <2 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+  %1 = add nsw <2 x i32> %x, <i32 20, i32 20>
+  %2 = add nsw <2 x i32> %y, <i32 57, i32 57>
+  %cmp = icmp sge <2 x i32> %1, %2
+  ret <2 x i1> %cmp
+}
+
+define <2 x i1> @icmp_add20_sge_add57_undef(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @icmp_add20_sge_add57_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = add nsw <2 x i32> [[X:%.*]], <i32 20, i32 20>
+; CHECK-NEXT:    [[TMP2:%.*]] = add nsw <2 x i32> [[Y:%.*]], <i32 57, i32 undef>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sge <2 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+  %1 = add nsw <2 x i32> %x, <i32 20, i32 20>
+  %2 = add nsw <2 x i32> %y, <i32 57, i32 undef>
+  %cmp = icmp sge <2 x i32> %1, %2
+  ret <2 x i1> %cmp
+}
+
+define <2 x i1> @icmp_add20_sge_add57_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @icmp_add20_sge_add57_vec_nonsplat(
+; CHECK-NEXT:    [[TMP1:%.*]] = add nsw <2 x i32> [[X:%.*]], <i32 20, i32 19>
+; CHECK-NEXT:    [[TMP2:%.*]] = add nsw <2 x i32> [[Y:%.*]], <i32 57, i32 58>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sge <2 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+  %1 = add nsw <2 x i32> %x, <i32 20, i32 19>
+  %2 = add nsw <2 x i32> %y, <i32 57, i32 58>
+  %cmp = icmp sge <2 x i32> %1, %2
+  ret <2 x i1> %cmp
+}
+
 define i1 @icmp_sub57_sge_sub20(i32 %x, i32 %y) {
 ; CHECK-LABEL: @icmp_sub57_sge_sub20(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add nsw i32 [[X:%.*]], -37
@@ -1591,6 +1630,45 @@ define i1 @icmp_sub57_sge_sub20(i32 %x, i32 %y) {
   ret i1 %cmp
 }
 
+define <2 x i1> @icmp_sub57_sge_sub20_splat(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @icmp_sub57_sge_sub20_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = add nsw <2 x i32> [[X:%.*]], <i32 -57, i32 -57>
+; CHECK-NEXT:    [[TMP2:%.*]] = add nsw <2 x i32> [[Y:%.*]], <i32 -20, i32 -20>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sge <2 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+  %1 = add nsw <2 x i32> %x, <i32 -57, i32 -57>
+  %2 = add nsw <2 x i32> %y, <i32 -20, i32 -20>
+  %cmp = icmp sge <2 x i32> %1, %2
+  ret <2 x i1> %cmp
+}
+
+define <2 x i1> @icmp_sub57_sge_sub20_vec_undef(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @icmp_sub57_sge_sub20_vec_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = add nsw <2 x i32> [[X:%.*]], <i32 -57, i32 undef>
+; CHECK-NEXT:    [[TMP2:%.*]] = add nsw <2 x i32> [[Y:%.*]], <i32 -20, i32 undef>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sge <2 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+  %1 = add nsw <2 x i32> %x, <i32 -57, i32 undef>
+  %2 = add nsw <2 x i32> %y, <i32 -20, i32 undef>
+  %cmp = icmp sge <2 x i32> %1, %2
+  ret <2 x i1> %cmp
+}
+
+define <2 x i1> @icmp_sub57_sge_sub20_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @icmp_sub57_sge_sub20_vec_nonsplat(
+; CHECK-NEXT:    [[TMP1:%.*]] = add nsw <2 x i32> [[X:%.*]], <i32 -57, i32 -58>
+; CHECK-NEXT:    [[TMP2:%.*]] = add nsw <2 x i32> [[Y:%.*]], <i32 -20, i32 -21>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sge <2 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+  %1 = add nsw <2 x i32> %x, <i32 -57, i32 -58>
+  %2 = add nsw <2 x i32> %y, <i32 -20, i32 -21>
+  %cmp = icmp sge <2 x i32> %1, %2
+  ret <2 x i1> %cmp
+}
+
 define i1 @icmp_and_shl_neg_ne_0(i32 %A, i32 %B) {
 ; CHECK-LABEL: @icmp_and_shl_neg_ne_0(
 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 1, [[B:%.*]]