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[X86] Regenerate vector shift tests. NFCI.
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Merge prefixes where possible, use 'X86' instead of 'X32' (which we try to only use for gnux32 triple tests).
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@RKSimon
RKSimon committed Oct 27, 2020
1 parent 0905bd5 commit 5a85555
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Showing 16 changed files with 532 additions and 715 deletions.
40 changes: 15 additions & 25 deletions llvm/test/CodeGen/X86/vec_shift.ll
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@@ -1,17 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64

define <2 x i64> @t1(<2 x i64> %b1, <2 x i64> %c) nounwind {
; X32-LABEL: t1:
; X32: # %bb.0: # %entry
; X32-NEXT: psllw %xmm1, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: t1:
; X64: # %bb.0: # %entry
; X64-NEXT: psllw %xmm1, %xmm0
; X64-NEXT: retq
; CHECK-LABEL: t1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psllw %xmm1, %xmm0
; CHECK-NEXT: ret{{[l|q]}}
entry:
%tmp6 = bitcast <2 x i64> %c to <8 x i16> ; <<8 x i16>> [#uses=1]
%tmp8 = bitcast <2 x i64> %b1 to <8 x i16> ; <<8 x i16>> [#uses=1]
Expand All @@ -21,11 +16,11 @@ entry:
}

define <2 x i64> @t3(<2 x i64> %b1, i32 %c) nounwind {
; X32-LABEL: t3:
; X32: # %bb.0: # %entry
; X32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X32-NEXT: psraw %xmm1, %xmm0
; X32-NEXT: retl
; X86-LABEL: t3:
; X86: # %bb.0: # %entry
; X86-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: psraw %xmm1, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: t3:
; X64: # %bb.0: # %entry
Expand All @@ -44,15 +39,10 @@ entry:
declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone

define <2 x i64> @t2(<2 x i64> %b1, <2 x i64> %c) nounwind {
; X32-LABEL: t2:
; X32: # %bb.0: # %entry
; X32-NEXT: psrlq %xmm1, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: t2:
; X64: # %bb.0: # %entry
; X64-NEXT: psrlq %xmm1, %xmm0
; X64-NEXT: retq
; CHECK-LABEL: t2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psrlq %xmm1, %xmm0
; CHECK-NEXT: ret{{[l|q]}}
entry:
%tmp9 = tail call <2 x i64> @llvm.x86.sse2.psrl.q( <2 x i64> %b1, <2 x i64> %c ) nounwind readnone ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp9
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36 changes: 12 additions & 24 deletions llvm/test/CodeGen/X86/vec_shift2.ll
View file
@@ -1,37 +1,25 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64

define <2 x i64> @t1(<2 x i64> %b1, <2 x i64> %c) nounwind {
; X32-LABEL: t1:
; X32: # %bb.0:
; X32-NEXT: psrlw $14, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: t1:
; X64: # %bb.0:
; X64-NEXT: psrlw $14, %xmm0
; X64-NEXT: retq
; CHECK-LABEL: t1:
; CHECK: # %bb.0:
; CHECK-NEXT: psrlw $14, %xmm0
; CHECK-NEXT: ret{{[l|q]}}
%tmp1 = bitcast <2 x i64> %b1 to <8 x i16>
%tmp2 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp1, <8 x i16> bitcast (<4 x i32> < i32 14, i32 undef, i32 undef, i32 undef > to <8 x i16>) ) nounwind readnone
%tmp3 = bitcast <8 x i16> %tmp2 to <2 x i64>
ret <2 x i64> %tmp3
}

define <4 x i32> @t2(<2 x i64> %b1, <2 x i64> %c) nounwind {
; X32-LABEL: t2:
; X32: # %bb.0:
; X32-NEXT: movl $14, %eax
; X32-NEXT: movd %eax, %xmm1
; X32-NEXT: pslld %xmm1, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: t2:
; X64: # %bb.0:
; X64-NEXT: movl $14, %eax
; X64-NEXT: movd %eax, %xmm1
; X64-NEXT: pslld %xmm1, %xmm0
; X64-NEXT: retq
; CHECK-LABEL: t2:
; CHECK: # %bb.0:
; CHECK-NEXT: movl $14, %eax
; CHECK-NEXT: movd %eax, %xmm1
; CHECK-NEXT: pslld %xmm1, %xmm0
; CHECK-NEXT: ret{{[l|q]}}
%tmp1 = bitcast <2 x i64> %b1 to <4 x i32>
%tmp2 = tail call <4 x i32> @llvm.x86.sse2.psll.d( <4 x i32> %tmp1, <4 x i32> < i32 14, i32 undef, i32 undef, i32 undef > ) nounwind readnone
ret <4 x i32> %tmp2
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37 changes: 16 additions & 21 deletions llvm/test/CodeGen/X86/vec_shift3.ll
View file
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64

define <2 x i64> @t1(<2 x i64> %x1, i32 %bits) nounwind {
; X32-LABEL: t1:
; X32: # %bb.0: # %entry
; X32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X32-NEXT: psllq %xmm1, %xmm0
; X32-NEXT: retl
; X86-LABEL: t1:
; X86: # %bb.0: # %entry
; X86-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: psllq %xmm1, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: t1:
; X64: # %bb.0: # %entry
Expand All @@ -20,26 +20,21 @@ entry:
}

define <2 x i64> @t2(<2 x i64> %x1) nounwind {
; X32-LABEL: t2:
; X32: # %bb.0: # %entry
; X32-NEXT: psllq $10, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: t2:
; X64: # %bb.0: # %entry
; X64-NEXT: psllq $10, %xmm0
; X64-NEXT: retq
; CHECK-LABEL: t2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psllq $10, %xmm0
; CHECK-NEXT: ret{{[l|q]}}
entry:
%tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 10 ) nounwind readnone ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp3
}

define <2 x i64> @t3(<2 x i64> %x1, i32 %bits) nounwind {
; X32-LABEL: t3:
; X32: # %bb.0: # %entry
; X32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X32-NEXT: psraw %xmm1, %xmm0
; X32-NEXT: retl
; X86-LABEL: t3:
; X86: # %bb.0: # %entry
; X86-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: psraw %xmm1, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: t3:
; X64: # %bb.0: # %entry
Expand Down
72 changes: 31 additions & 41 deletions llvm/test/CodeGen/X86/vec_shift4.ll
View file
@@ -1,15 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,X86
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,X64

define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
; X32-LABEL: shl1:
; X32: # %bb.0: # %entry
; X32-NEXT: pslld $23, %xmm1
; X32-NEXT: paddd {{\.LCPI.*}}, %xmm1
; X32-NEXT: cvttps2dq %xmm1, %xmm1
; X32-NEXT: pmulld %xmm1, %xmm0
; X32-NEXT: retl
; X86-LABEL: shl1:
; X86: # %bb.0: # %entry
; X86-NEXT: pslld $23, %xmm1
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm1
; X86-NEXT: cvttps2dq %xmm1, %xmm1
; X86-NEXT: pmulld %xmm1, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: shl1:
; X64: # %bb.0: # %entry
Expand All @@ -19,40 +19,34 @@ define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
; X64-NEXT: pmulld %xmm1, %xmm0
; X64-NEXT: retq
entry:
; CHECK-NOT: shll
; CHECK: pslld
; CHECK: paddd
; CHECK: cvttps2dq
; CHECK: pmulld

%shl = shl <4 x i32> %r, %a ; <<4 x i32>> [#uses=1]
%tmp2 = bitcast <4 x i32> %shl to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp2
}

define <2 x i64> @shl2(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp {
; X32-LABEL: shl2:
; X32: # %bb.0: # %entry
; X32-NEXT: movdqa %xmm0, %xmm2
; X32-NEXT: psllw $5, %xmm1
; X32-NEXT: movdqa %xmm0, %xmm3
; X32-NEXT: psllw $4, %xmm3
; X32-NEXT: pand {{\.LCPI.*}}, %xmm3
; X32-NEXT: movdqa %xmm1, %xmm0
; X32-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; X32-NEXT: movdqa %xmm2, %xmm3
; X32-NEXT: psllw $2, %xmm3
; X32-NEXT: pand {{\.LCPI.*}}, %xmm3
; X32-NEXT: paddb %xmm1, %xmm1
; X32-NEXT: movdqa %xmm1, %xmm0
; X32-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; X32-NEXT: movdqa %xmm2, %xmm3
; X32-NEXT: paddb %xmm2, %xmm3
; X32-NEXT: paddb %xmm1, %xmm1
; X32-NEXT: movdqa %xmm1, %xmm0
; X32-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; X32-NEXT: movdqa %xmm2, %xmm0
; X32-NEXT: retl
; X86-LABEL: shl2:
; X86: # %bb.0: # %entry
; X86-NEXT: movdqa %xmm0, %xmm2
; X86-NEXT: psllw $5, %xmm1
; X86-NEXT: movdqa %xmm0, %xmm3
; X86-NEXT: psllw $4, %xmm3
; X86-NEXT: pand {{\.LCPI.*}}, %xmm3
; X86-NEXT: movdqa %xmm1, %xmm0
; X86-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; X86-NEXT: movdqa %xmm2, %xmm3
; X86-NEXT: psllw $2, %xmm3
; X86-NEXT: pand {{\.LCPI.*}}, %xmm3
; X86-NEXT: paddb %xmm1, %xmm1
; X86-NEXT: movdqa %xmm1, %xmm0
; X86-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; X86-NEXT: movdqa %xmm2, %xmm3
; X86-NEXT: paddb %xmm2, %xmm3
; X86-NEXT: paddb %xmm1, %xmm1
; X86-NEXT: movdqa %xmm1, %xmm0
; X86-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; X86-NEXT: movdqa %xmm2, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: shl2:
; X64: # %bb.0: # %entry
Expand All @@ -77,10 +71,6 @@ define <2 x i64> @shl2(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp {
; X64-NEXT: movdqa %xmm2, %xmm0
; X64-NEXT: retq
entry:
; CHECK-NOT: shlb
; CHECK: pblendvb
; CHECK: pblendvb
; CHECK: pblendvb
%shl = shl <16 x i8> %r, %a ; <<16 x i8>> [#uses=1]
%tmp2 = bitcast <16 x i8> %shl to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp2
Expand Down

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