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TableGen: Fix infinite recursion in RegisterBankEmitter
Summary: AMDGPU has two register classes with the same set of registers, and this was causing this tablegen backend would get stuck in infinite recursion. Reviewers: dsanders Reviewed By: dsanders Subscribers: tpr, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D29049 llvm-svn: 293483
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Original file line number | Diff line number | Diff line change |
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// RUN: llvm-tblgen -gen-register-bank -I %p/../../include %s | FileCheck %s | ||
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include "llvm/Target/Target.td" | ||
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def MyTarget : Target; | ||
def R0 : Register<"r0">; | ||
let Size = 32 in { | ||
def ClassA : RegisterClass<"MyTarget", [i32], 32, (add R0)>; | ||
def ClassB : RegisterClass<"MyTarget", [i1], 32, (add ClassA)>; | ||
} | ||
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// CHECK: GPRRegBankCoverageData | ||
// CHECK: MyTarget::ClassARegClassID | ||
// CHECK: MyTarget::ClassBRegClassID | ||
def GPRRegBank : RegisterBank<"GPR", [ClassA]>; |
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