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[unittests][CodeGen] Mark tests that cannot be executed with GTEST_SK…
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…IP()

This helps to distinguish such tests from successfully passed ones.

Differential Revision: https://reviews.llvm.org/D102754
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@igorkudrin
igorkudrin committed May 21, 2021
1 parent 21b40f0 commit 5bbf1fe
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Showing 7 changed files with 30 additions and 137 deletions.
77 changes: 2 additions & 75 deletions llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp
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Expand Up @@ -37,14 +37,14 @@ class AArch64SelectionDAGTest : public testing::Test {
// initialize a target. A skeleton Target for unittests would allow us to
// always run these tests.
if (!T)
return;
GTEST_SKIP();

TargetOptions Options;
TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
T->createTargetMachine("AArch64", "", "+sve", Options, None, None,
CodeGenOpt::Aggressive)));
if (!TM)
return;
GTEST_SKIP();

SMDiagnostic SMError;
M = parseAssemblyString(Assembly, SMError, Context);
Expand Down Expand Up @@ -85,8 +85,6 @@ class AArch64SelectionDAGTest : public testing::Test {
};

TEST_F(AArch64SelectionDAGTest, computeKnownBits_ZERO_EXTEND_VECTOR_INREG) {
if (!TM)
return;
SDLoc Loc;
auto Int8VT = EVT::getIntegerVT(Context, 8);
auto Int16VT = EVT::getIntegerVT(Context, 16);
Expand All @@ -100,8 +98,6 @@ TEST_F(AArch64SelectionDAGTest, computeKnownBits_ZERO_EXTEND_VECTOR_INREG) {
}

TEST_F(AArch64SelectionDAGTest, computeKnownBitsSVE_ZERO_EXTEND_VECTOR_INREG) {
if (!TM)
return;
SDLoc Loc;
auto Int8VT = EVT::getIntegerVT(Context, 8);
auto Int16VT = EVT::getIntegerVT(Context, 16);
Expand All @@ -119,8 +115,6 @@ TEST_F(AArch64SelectionDAGTest, computeKnownBitsSVE_ZERO_EXTEND_VECTOR_INREG) {
}

TEST_F(AArch64SelectionDAGTest, computeKnownBits_EXTRACT_SUBVECTOR) {
if (!TM)
return;
SDLoc Loc;
auto IntVT = EVT::getIntegerVT(Context, 8);
auto VecVT = EVT::getVectorVT(Context, IntVT, 3);
Expand All @@ -134,8 +128,6 @@ TEST_F(AArch64SelectionDAGTest, computeKnownBits_EXTRACT_SUBVECTOR) {
}

TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_SIGN_EXTEND_VECTOR_INREG) {
if (!TM)
return;
SDLoc Loc;
auto Int8VT = EVT::getIntegerVT(Context, 8);
auto Int16VT = EVT::getIntegerVT(Context, 16);
Expand All @@ -148,8 +140,6 @@ TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_SIGN_EXTEND_VECTOR_INREG) {
}

TEST_F(AArch64SelectionDAGTest, ComputeNumSignBitsSVE_SIGN_EXTEND_VECTOR_INREG) {
if (!TM)
return;
SDLoc Loc;
auto Int8VT = EVT::getIntegerVT(Context, 8);
auto Int16VT = EVT::getIntegerVT(Context, 16);
Expand All @@ -162,8 +152,6 @@ TEST_F(AArch64SelectionDAGTest, ComputeNumSignBitsSVE_SIGN_EXTEND_VECTOR_INREG)
}

TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_EXTRACT_SUBVECTOR) {
if (!TM)
return;
SDLoc Loc;
auto IntVT = EVT::getIntegerVT(Context, 8);
auto VecVT = EVT::getVectorVT(Context, IntVT, 3);
Expand All @@ -176,9 +164,6 @@ TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_EXTRACT_SUBVECTOR) {
}

TEST_F(AArch64SelectionDAGTest, SimplifyDemandedVectorElts_EXTRACT_SUBVECTOR) {
if (!TM)
return;

TargetLowering TL(*TM);

SDLoc Loc;
Expand All @@ -198,9 +183,6 @@ TEST_F(AArch64SelectionDAGTest, SimplifyDemandedVectorElts_EXTRACT_SUBVECTOR) {
}

TEST_F(AArch64SelectionDAGTest, SimplifyDemandedBitsNEON) {
if (!TM)
return;

TargetLowering TL(*TM);

SDLoc Loc;
Expand All @@ -227,9 +209,6 @@ TEST_F(AArch64SelectionDAGTest, SimplifyDemandedBitsNEON) {
}

TEST_F(AArch64SelectionDAGTest, SimplifyDemandedBitsSVE) {
if (!TM)
return;

TargetLowering TL(*TM);

SDLoc Loc;
Expand All @@ -254,8 +233,6 @@ TEST_F(AArch64SelectionDAGTest, SimplifyDemandedBitsSVE) {

// Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits.
TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_ADD) {
if (!TM)
return;
SDLoc Loc;
auto IntVT = EVT::getIntegerVT(Context, 8);
auto UnknownOp = DAG->getRegister(0, IntVT);
Expand All @@ -275,8 +252,6 @@ TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_ADD) {

// Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits.
TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_SUB) {
if (!TM)
return;
SDLoc Loc;
auto IntVT = EVT::getIntegerVT(Context, 8);
auto N0 = DAG->getConstant(0x55, Loc, IntVT);
Expand All @@ -295,9 +270,6 @@ TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_SUB) {
}

TEST_F(AArch64SelectionDAGTest, isSplatValue_Fixed_BUILD_VECTOR) {
if (!TM)
return;

TargetLowering TL(*TM);

SDLoc Loc;
Expand All @@ -318,9 +290,6 @@ TEST_F(AArch64SelectionDAGTest, isSplatValue_Fixed_BUILD_VECTOR) {
}

TEST_F(AArch64SelectionDAGTest, isSplatValue_Fixed_ADD_of_BUILD_VECTOR) {
if (!TM)
return;

TargetLowering TL(*TM);

SDLoc Loc;
Expand All @@ -345,9 +314,6 @@ TEST_F(AArch64SelectionDAGTest, isSplatValue_Fixed_ADD_of_BUILD_VECTOR) {
}

TEST_F(AArch64SelectionDAGTest, isSplatValue_Scalable_SPLAT_VECTOR) {
if (!TM)
return;

TargetLowering TL(*TM);

SDLoc Loc;
Expand All @@ -368,9 +334,6 @@ TEST_F(AArch64SelectionDAGTest, isSplatValue_Scalable_SPLAT_VECTOR) {
}

TEST_F(AArch64SelectionDAGTest, isSplatValue_Scalable_ADD_of_SPLAT_VECTOR) {
if (!TM)
return;

TargetLowering TL(*TM);

SDLoc Loc;
Expand All @@ -395,9 +358,6 @@ TEST_F(AArch64SelectionDAGTest, isSplatValue_Scalable_ADD_of_SPLAT_VECTOR) {
}

TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Fixed_BUILD_VECTOR) {
if (!TM)
return;

TargetLowering TL(*TM);

SDLoc Loc;
Expand All @@ -413,9 +373,6 @@ TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Fixed_BUILD_VECTOR) {
}

TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Fixed_ADD_of_BUILD_VECTOR) {
if (!TM)
return;

TargetLowering TL(*TM);

SDLoc Loc;
Expand All @@ -434,9 +391,6 @@ TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Fixed_ADD_of_BUILD_VECTOR)
}

TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Scalable_SPLAT_VECTOR) {
if (!TM)
return;

TargetLowering TL(*TM);

SDLoc Loc;
Expand All @@ -452,9 +406,6 @@ TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Scalable_SPLAT_VECTOR) {
}

TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Scalable_ADD_of_SPLAT_VECTOR) {
if (!TM)
return;

TargetLowering TL(*TM);

SDLoc Loc;
Expand All @@ -473,9 +424,6 @@ TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Scalable_ADD_of_SPLAT_VECTO
}

TEST_F(AArch64SelectionDAGTest, getRepeatedSequence_Patterns) {
if (!TM)
return;

TargetLowering TL(*TM);

SDLoc Loc;
Expand Down Expand Up @@ -594,45 +542,30 @@ TEST_F(AArch64SelectionDAGTest, getRepeatedSequence_Patterns) {
}

TEST_F(AArch64SelectionDAGTest, getTypeConversion_SplitScalableMVT) {
if (!TM)
return;

MVT VT = MVT::nxv4i64;
EXPECT_EQ(getTypeAction(VT), TargetLoweringBase::TypeSplitVector);
ASSERT_TRUE(getTypeToTransformTo(VT).isScalableVector());
}

TEST_F(AArch64SelectionDAGTest, getTypeConversion_PromoteScalableMVT) {
if (!TM)
return;

MVT VT = MVT::nxv2i32;
EXPECT_EQ(getTypeAction(VT), TargetLoweringBase::TypePromoteInteger);
ASSERT_TRUE(getTypeToTransformTo(VT).isScalableVector());
}

TEST_F(AArch64SelectionDAGTest, getTypeConversion_NoScalarizeMVT_nxv1f32) {
if (!TM)
return;

MVT VT = MVT::nxv1f32;
EXPECT_NE(getTypeAction(VT), TargetLoweringBase::TypeScalarizeVector);
ASSERT_TRUE(getTypeToTransformTo(VT).isScalableVector());
}

TEST_F(AArch64SelectionDAGTest, getTypeConversion_SplitScalableEVT) {
if (!TM)
return;

EVT VT = EVT::getVectorVT(Context, MVT::i64, 256, true);
EXPECT_EQ(getTypeAction(VT), TargetLoweringBase::TypeSplitVector);
EXPECT_EQ(getTypeToTransformTo(VT), VT.getHalfNumVectorElementsVT(Context));
}

TEST_F(AArch64SelectionDAGTest, getTypeConversion_WidenScalableEVT) {
if (!TM)
return;

EVT FromVT = EVT::getVectorVT(Context, MVT::i64, 6, true);
EVT ToVT = EVT::getVectorVT(Context, MVT::i64, 8, true);

Expand All @@ -641,17 +574,11 @@ TEST_F(AArch64SelectionDAGTest, getTypeConversion_WidenScalableEVT) {
}

TEST_F(AArch64SelectionDAGTest, getTypeConversion_NoScalarizeEVT_nxv1f128) {
if (!TM)
return;

EVT FromVT = EVT::getVectorVT(Context, MVT::f128, 1, true);
EXPECT_DEATH(getTypeAction(FromVT), "Cannot legalize this vector");
}

TEST_F(AArch64SelectionDAGTest, TestFold_STEP_VECTOR) {
if (!TM)
return;

SDLoc Loc;
auto IntVT = EVT::getIntegerVT(Context, 8);
auto VecVT = EVT::getVectorVT(Context, MVT::i8, 16, true);
Expand Down

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