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[ARM][Asm] Accept upper case coprocessor number and registers
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Differential revision: https://reviews.llvm.org/D59760

llvm-svn: 356984
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@ostannard
ostannard committed Mar 26, 2019
1 parent 90dbbdb commit 5c90238
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Showing 3 changed files with 58 additions and 2 deletions.
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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Expand Up @@ -3661,7 +3661,7 @@ ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
if (Tok.isNot(AsmToken::Identifier))
return MatchOperand_NoMatch;

int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
int Num = MatchCoprocessorOperandName(Tok.getString().lower(), 'p');
if (Num == -1)
return MatchOperand_NoMatch;
// ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
Expand All @@ -3684,7 +3684,7 @@ ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
if (Tok.isNot(AsmToken::Identifier))
return MatchOperand_NoMatch;

int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
int Reg = MatchCoprocessorOperandName(Tok.getString().lower(), 'c');
if (Reg == -1)
return MatchOperand_NoMatch;

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28 changes: 28 additions & 0 deletions llvm/test/MC/ARM/basic-arm-instructions.s
View file
Expand Up @@ -1244,23 +1244,35 @@ Lforward:
@------------------------------------------------------------------------------
mcr p7, #1, r5, c1, c1, #4
mcr2 p7, #1, r5, c1, c1, #4
MCR P7, #1, R5, C1, C1, #4
MCR2 P7, #1, R5, C1, C1, #4

@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xee]
@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe]
@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xee]
@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe]

mcrls p7, #1, r5, c1, c1, #4
MCRLS P7, #1, R5, C1, C1, #4
@ CHECK: mcrls p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0x9e]
@ CHECK: mcrls p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0x9e]

@------------------------------------------------------------------------------
@ MCRR/MCRR2
@------------------------------------------------------------------------------
mcrr p7, #15, r5, r4, c1
mcrr2 p7, #15, r5, r4, c1
MCRR P7, #15, R5, R4, C1
MCRR2 P7, #15, R5, R4, C1

@ CHECK: mcrr p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xec]
@ CHECK: mcrr2 p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xfc]
@ CHECK: mcrr p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xec]
@ CHECK: mcrr2 p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xfc]

mcrrgt p7, #15, r5, r4, c1
MCRRGT P7, #15, R5, R4, C1
@ CHECK: mcrrgt p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xcc]
@ CHECK: mcrrgt p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xcc]

@------------------------------------------------------------------------------
Expand Down Expand Up @@ -1385,25 +1397,41 @@ Lforward:
mrc p15, #7, apsr_nzcv, c15, c6, #6
mrc2 p14, #0, r1, c1, c2, #4
mrc2 p9, #7, apsr_nzcv, c15, c0, #1
MRC P14, #0, R1, C1, C2, #4
MRC P15, #7, APSR_NZCV, C15, C6, #6
MRC2 P14, #0, R1, C1, C2, #4
MRC2 P9, #7, APSR_NZCV, C15, C0, #1

@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee]
@ CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0xee]
@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
@ CHECK: mrc2 p9, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xf9,0xff,0xfe]
@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee]
@ CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0xee]
@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
@ CHECK: mrc2 p9, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xf9,0xff,0xfe]

mrceq p15, #7, apsr_nzcv, c15, c6, #6
MRCEQ P15, #7, APSR_NZCV, C15, C6, #6
@ CHECK: mrceq p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0x0e]
@ CHECK: mrceq p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0x0e]

@------------------------------------------------------------------------------
@ MRRC/MRRC2
@------------------------------------------------------------------------------
mrrc p7, #1, r5, r4, c1
mrrc2 p7, #1, r5, r4, c1
MRRC P7, #1, R5, R4, C1
MRRC2 P7, #1, R5, R4, C1

@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec]
@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc]
@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec]
@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc]

mrrclo p7, #1, r5, r4, c1
MRRCLO P7, #1, R5, R4, C1
@ CHECK: mrrclo p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0x3c]
@ CHECK: mrrclo p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0x3c]

@------------------------------------------------------------------------------
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28 changes: 28 additions & 0 deletions llvm/test/MC/ARM/basic-thumb2-instructions.s
View file
Expand Up @@ -1409,21 +1409,33 @@ _func:
mcr2 p7, #1, r5, c1, c1, #4
mcr p14, #0, r4, c0, c5
mcr2 p4, #2, r2, c1, c3
MCR P7, #1, R5, C1, C1, #4
MCR2 P7, #1, R5, C1, C1, #4
MCR P14, #0, R4, C0, C5
MCR2 P4, #2, R2, C1, C3

@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xee,0x91,0x57]
@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xfe,0x91,0x57]
@ CHECK: mcr p14, #0, r4, c0, c5, #0 @ encoding: [0x00,0xee,0x15,0x4e]
@ CHECK: mcr2 p4, #2, r2, c1, c3, #0 @ encoding: [0x41,0xfe,0x13,0x24]
@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xee,0x91,0x57]
@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xfe,0x91,0x57]
@ CHECK: mcr p14, #0, r4, c0, c5, #0 @ encoding: [0x00,0xee,0x15,0x4e]
@ CHECK: mcr2 p4, #2, r2, c1, c3, #0 @ encoding: [0x41,0xfe,0x13,0x24]


@------------------------------------------------------------------------------
@ MCRR/MCRR2
@------------------------------------------------------------------------------
mcrr p7, #15, r5, r4, c1
mcrr2 p7, #15, r5, r4, c1
MCRR P7, #15, R5, R4, C1
MCRR2 P7, #15, R5, R4, C1

@ CHECK: mcrr p7, #15, r5, r4, c1 @ encoding: [0x44,0xec,0xf1,0x57]
@ CHECK: mcrr2 p7, #15, r5, r4, c1 @ encoding: [0x44,0xfc,0xf1,0x57]
@ CHECK: mcrr p7, #15, r5, r4, c1 @ encoding: [0x44,0xec,0xf1,0x57]
@ CHECK: mcrr2 p7, #15, r5, r4, c1 @ encoding: [0x44,0xfc,0xf1,0x57]


@------------------------------------------------------------------------------
Expand Down Expand Up @@ -1571,22 +1583,38 @@ _func:
mrc2 p12, #3, r3, c3, c4
mrc2 p14, #0, r1, c1, c2, #4
mrc2 p8, #7, apsr_nzcv, c15, c0, #1
MRC P14, #0, R1, C1, C2, #4
MRC P15, #7, APSR_NZCV, C15, C6, #6
MRC P9, #1, R1, C2, C2
MRC2 P12, #3, R3, C3, C4
MRC2 P14, #0, R1, C1, C2, #4
MRC2 P8, #7, APSR_NZCV, C15, C0, #1

@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xee,0x92,0x1e]
@ CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xff,0xee,0xd6,0xff]
@ CHECK: mrc p9, #1, r1, c2, c2, #0 @ encoding: [0x32,0xee,0x12,0x19]
@ CHECK: mrc2 p12, #3, r3, c3, c4, #0 @ encoding: [0x73,0xfe,0x14,0x3c]
@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e]
@ CHECK: mrc2 p8, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0xff,0xfe,0x30,0xf8]
@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xee,0x92,0x1e]
@ CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xff,0xee,0xd6,0xff]
@ CHECK: mrc p9, #1, r1, c2, c2, #0 @ encoding: [0x32,0xee,0x12,0x19]
@ CHECK: mrc2 p12, #3, r3, c3, c4, #0 @ encoding: [0x73,0xfe,0x14,0x3c]
@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e]
@ CHECK: mrc2 p8, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0xff,0xfe,0x30,0xf8]

@------------------------------------------------------------------------------
@ MRRC/MRRC2
@------------------------------------------------------------------------------
mrrc p7, #1, r5, r4, c1
mrrc2 p7, #1, r5, r4, c1
MRRC P7, #1, R5, R4, C1
MRRC2 P7, #1, R5, R4, C1

@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x54,0xec,0x11,0x57]
@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x54,0xfc,0x11,0x57]
@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x54,0xec,0x11,0x57]
@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x54,0xfc,0x11,0x57]


@------------------------------------------------------------------------------
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