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[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHaza…
…rdRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards(). Differential Revision: https://reviews.llvm.org/D40098 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320083 91177308-0d34-0410-b5e6-96231b3b80d8
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# RUN: llc -mcpu=gfx900 -march=amdgcn -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck %s | ||
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# If an INLINEASM statement is preceded by a vmem store of more than 8 bytes *and* | ||
# the INLINEASM defs the vregs holding the data-to-be-stored by that preceding store, | ||
# then the hazard recognizer should insert a s_nop in between them. | ||
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... | ||
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# GCN-LABEL: name: hazard-inlineasm | ||
# CHECK: FLAT_STORE_DWORDX4 | ||
# CHECK-NEXT: S_NOP 0 | ||
# CHECK-NEXT: INLINEASM | ||
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--- | ||
name: hazard-inlineasm | ||
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body: | | ||
bb.0: | ||
FLAT_STORE_DWORDX4 %vgpr49_vgpr50, %vgpr26_vgpr27_vgpr28_vgpr29, 0, 0, 0, implicit %exec, implicit %flat_scr | ||
INLINEASM $"v_mad_u64_u32 $0, $1, $2, $3, $4", 0, 2621450, def %vgpr26_vgpr27, 2818058, def dead %sgpr14_sgpr15, 589833, %sgpr12, 327689, killed %vgpr51, 2621449, %vgpr46_vgpr47 | ||
S_ENDPGM | ||
... | ||
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