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[RISCV] Enable shrink wrap by default
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Differential Revision: https://reviews.llvm.org/D109037
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Evandro Menezes committed Sep 2, 2021
1 parent e4e69ba commit 5ebdb07
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Showing 11 changed files with 338 additions and 521 deletions.
8 changes: 8 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
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Expand Up @@ -1087,6 +1087,14 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters(
return true;
}

bool RISCVFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {
// Keep the conventional code flow when not optimizing.
if (MF.getFunction().hasOptNone())
return false;

return true;
}

bool RISCVFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const {
MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
const MachineFunction *MF = MBB.getParent();
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2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.h
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Expand Up @@ -65,6 +65,8 @@ class RISCVFrameLowering : public TargetFrameLowering {
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override;

bool enableShrinkWrapping(const MachineFunction &MF) const override;

bool isSupportedStackID(TargetStackID::Value ID) const override;
TargetStackID::Value getStackIDForScalableVectors() const override;

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99 changes: 45 additions & 54 deletions llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
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Expand Up @@ -137,11 +137,11 @@ define i64 @test_bswap_i64(i64 %a) nounwind {
define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-LABEL: test_cttz_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a1, a0, 255
; RV32I-NEXT: beqz a1, .LBB3_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
Expand All @@ -165,21 +165,20 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB3_3
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: addi a0, zero, 8
; RV32I-NEXT: .LBB3_3: # %cond.end
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: addi a0, zero, 8
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_cttz_i8:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: andi a1, a0, 255
; RV64I-NEXT: beqz a1, .LBB3_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, a0, -1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1
Expand Down Expand Up @@ -225,12 +224,11 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: j .LBB3_3
; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: addi a0, zero, 8
; RV64I-NEXT: .LBB3_3: # %cond.end
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: addi a0, zero, 8
; RV64I-NEXT: ret
%tmp = call i8 @llvm.cttz.i8(i8 %a, i1 false)
ret i8 %tmp
Expand All @@ -239,13 +237,13 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-LABEL: test_cttz_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a1, a0, a1
; RV32I-NEXT: beqz a1, .LBB4_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
Expand All @@ -269,23 +267,22 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB4_3
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: addi a0, zero, 16
; RV32I-NEXT: .LBB4_3: # %cond.end
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: addi a0, zero, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_cttz_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: beqz a1, .LBB4_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, a0, -1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1
Expand Down Expand Up @@ -331,12 +328,11 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: j .LBB4_3
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: addi a0, zero, 16
; RV64I-NEXT: .LBB4_3: # %cond.end
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: addi a0, zero, 16
; RV64I-NEXT: ret
%tmp = call i16 @llvm.cttz.i16(i16 %a, i1 false)
ret i16 %tmp
Expand All @@ -345,10 +341,10 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-LABEL: test_cttz_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz a0, .LBB5_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
Expand All @@ -372,21 +368,20 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB5_3
; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB5_3: # %cond.end
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_cttz_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a1, a0
; RV64I-NEXT: beqz a1, .LBB5_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, a0, -1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1
Expand Down Expand Up @@ -432,12 +427,11 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: j .LBB5_3
; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: .LBB5_3: # %cond.end
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: ret
%tmp = call i32 @llvm.cttz.i32(i32 %a, i1 false)
ret i32 %tmp
Expand All @@ -446,10 +440,10 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-LABEL: test_ctlz_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz a0, .LBB6_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 2
Expand Down Expand Up @@ -481,21 +475,20 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB6_3
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB6_3: # %cond.end
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_ctlz_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a1, a0
; RV64I-NEXT: beqz a1, .LBB6_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
Expand Down Expand Up @@ -554,12 +547,11 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: addi a0, a0, -32
; RV64I-NEXT: j .LBB6_3
; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: .LBB6_3: # %cond.end
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: ret
%tmp = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
ret i32 %tmp
Expand Down Expand Up @@ -640,10 +632,10 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
;
; RV64I-LABEL: test_cttz_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: beqz a0, .LBB7_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, a0, -1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1
Expand Down Expand Up @@ -689,12 +681,11 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: j .LBB7_3
; RV64I-NEXT: .LBB7_2:
; RV64I-NEXT: addi a0, zero, 64
; RV64I-NEXT: .LBB7_3: # %cond.end
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB7_2:
; RV64I-NEXT: addi a0, zero, 64
; RV64I-NEXT: ret
%tmp = call i64 @llvm.cttz.i64(i64 %a, i1 false)
ret i64 %tmp
Expand Down

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