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[clang][CodeGen] Emit atomic IR in place of optimized libcalls. (#73176)
In the beginning, Clang only emitted atomic IR for operations it knew the underlying microarch had instructions for, meaning it required significant knowledge of the target. Later, the backend acquired the ability to lower IR to libcalls. To avoid duplicating logic and improve logic locality, we'd like to move as much as possible to the backend. There are many ways to describe this change. For example, this change reduces the variables Clang uses to decide whether to emit libcalls or IR, down to only the atomic's size.
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| Original file line number | Diff line number | Diff line change |
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| @@ -1,68 +1,34 @@ | ||
| // RUN: %clang_cc1 -triple riscv32 -O1 -emit-llvm %s -o - \ | ||
| // RUN: | FileCheck %s -check-prefix=RV32I | ||
| // RUN: -verify=no-atomics | ||
| // RUN: %clang_cc1 -triple riscv32 -target-feature +a -O1 -emit-llvm %s -o - \ | ||
| // RUN: | FileCheck %s -check-prefix=RV32IA | ||
| // RUN: -verify=small-atomics | ||
| // RUN: %clang_cc1 -triple riscv64 -O1 -emit-llvm %s -o - \ | ||
| // RUN: | FileCheck %s -check-prefix=RV64I | ||
| // RUN: -verify=no-atomics | ||
| // RUN: %clang_cc1 -triple riscv64 -target-feature +a -O1 -emit-llvm %s -o - \ | ||
| // RUN: | FileCheck %s -check-prefix=RV64IA | ||
| // RUN: -verify=all-atomics | ||
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| // This test demonstrates that MaxAtomicInlineWidth is set appropriately when | ||
| // the atomics instruction set extension is enabled. | ||
| // all-atomics-no-diagnostics | ||
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| #include <stdatomic.h> | ||
| #include <stdint.h> | ||
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| void test_i8_atomics(_Atomic(int8_t) * a, int8_t b) { | ||
| // RV32I: call zeroext i8 @__atomic_load_1 | ||
| // RV32I: call void @__atomic_store_1 | ||
| // RV32I: call zeroext i8 @__atomic_fetch_add_1 | ||
| // RV32IA: load atomic i8, ptr %a seq_cst, align 1 | ||
| // RV32IA: store atomic i8 %b, ptr %a seq_cst, align 1 | ||
| // RV32IA: atomicrmw add ptr %a, i8 %b seq_cst, align 1 | ||
| // RV64I: call zeroext i8 @__atomic_load_1 | ||
| // RV64I: call void @__atomic_store_1 | ||
| // RV64I: call zeroext i8 @__atomic_fetch_add_1 | ||
| // RV64IA: load atomic i8, ptr %a seq_cst, align 1 | ||
| // RV64IA: store atomic i8 %b, ptr %a seq_cst, align 1 | ||
| // RV64IA: atomicrmw add ptr %a, i8 %b seq_cst, align 1 | ||
| __c11_atomic_load(a, memory_order_seq_cst); | ||
| __c11_atomic_store(a, b, memory_order_seq_cst); | ||
| __c11_atomic_fetch_add(a, b, memory_order_seq_cst); | ||
| __c11_atomic_load(a, memory_order_seq_cst); // no-atomics-warning {{large atomic operation may incur significant performance penalty; the access size (1 bytes) exceeds the max lock-free size (0 bytes)}} | ||
| __c11_atomic_store(a, b, memory_order_seq_cst); // no-atomics-warning {{large atomic operation may incur significant performance penalty; the access size (1 bytes) exceeds the max lock-free size (0 bytes)}} | ||
| __c11_atomic_fetch_add(a, b, memory_order_seq_cst); // no-atomics-warning {{large atomic operation may incur significant performance penalty; the access size (1 bytes) exceeds the max lock-free size (0 bytes)}} | ||
| } | ||
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| void test_i32_atomics(_Atomic(int32_t) * a, int32_t b) { | ||
| // RV32I: call i32 @__atomic_load_4 | ||
| // RV32I: call void @__atomic_store_4 | ||
| // RV32I: call i32 @__atomic_fetch_add_4 | ||
| // RV32IA: load atomic i32, ptr %a seq_cst, align 4 | ||
| // RV32IA: store atomic i32 %b, ptr %a seq_cst, align 4 | ||
| // RV32IA: atomicrmw add ptr %a, i32 %b seq_cst, align 4 | ||
| // RV64I: call signext i32 @__atomic_load_4 | ||
| // RV64I: call void @__atomic_store_4 | ||
| // RV64I: call signext i32 @__atomic_fetch_add_4 | ||
| // RV64IA: load atomic i32, ptr %a seq_cst, align 4 | ||
| // RV64IA: store atomic i32 %b, ptr %a seq_cst, align 4 | ||
| // RV64IA: atomicrmw add ptr %a, i32 %b seq_cst, align 4 | ||
| __c11_atomic_load(a, memory_order_seq_cst); | ||
| __c11_atomic_store(a, b, memory_order_seq_cst); | ||
| __c11_atomic_fetch_add(a, b, memory_order_seq_cst); | ||
| __c11_atomic_load(a, memory_order_seq_cst); // no-atomics-warning {{large atomic operation may incur significant performance penalty; the access size (4 bytes) exceeds the max lock-free size (0 bytes)}} | ||
| __c11_atomic_store(a, b, memory_order_seq_cst); // no-atomics-warning {{large atomic operation may incur significant performance penalty; the access size (4 bytes) exceeds the max lock-free size (0 bytes)}} | ||
| __c11_atomic_fetch_add(a, b, memory_order_seq_cst); // no-atomics-warning {{large atomic operation may incur significant performance penalty; the access size (4 bytes) exceeds the max lock-free size (0 bytes)}} | ||
| } | ||
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| void test_i64_atomics(_Atomic(int64_t) * a, int64_t b) { | ||
| // RV32I: call i64 @__atomic_load_8 | ||
| // RV32I: call void @__atomic_store_8 | ||
| // RV32I: call i64 @__atomic_fetch_add_8 | ||
| // RV32IA: call i64 @__atomic_load_8 | ||
| // RV32IA: call void @__atomic_store_8 | ||
| // RV32IA: call i64 @__atomic_fetch_add_8 | ||
| // RV64I: call i64 @__atomic_load_8 | ||
| // RV64I: call void @__atomic_store_8 | ||
| // RV64I: call i64 @__atomic_fetch_add_8 | ||
| // RV64IA: load atomic i64, ptr %a seq_cst, align 8 | ||
| // RV64IA: store atomic i64 %b, ptr %a seq_cst, align 8 | ||
| // RV64IA: atomicrmw add ptr %a, i64 %b seq_cst, align 8 | ||
| __c11_atomic_load(a, memory_order_seq_cst); | ||
| __c11_atomic_store(a, b, memory_order_seq_cst); | ||
| __c11_atomic_fetch_add(a, b, memory_order_seq_cst); | ||
| __c11_atomic_load(a, memory_order_seq_cst); // no-atomics-warning {{large atomic operation may incur significant performance penalty; the access size (8 bytes) exceeds the max lock-free size (0 bytes)}} | ||
| // small-atomics-warning@28 {{large atomic operation may incur significant performance penalty; the access size (8 bytes) exceeds the max lock-free size (4 bytes)}} | ||
| __c11_atomic_store(a, b, memory_order_seq_cst); // no-atomics-warning {{large atomic operation may incur significant performance penalty; the access size (8 bytes) exceeds the max lock-free size (0 bytes)}} | ||
| // small-atomics-warning@30 {{large atomic operation may incur significant performance penalty; the access size (8 bytes) exceeds the max lock-free size (4 bytes)}} | ||
| __c11_atomic_fetch_add(a, b, memory_order_seq_cst); // no-atomics-warning {{large atomic operation may incur significant performance penalty; the access size (8 bytes) exceeds the max lock-free size (0 bytes)}} | ||
| // small-atomics-warning@32 {{large atomic operation may incur significant performance penalty; the access size (8 bytes) exceeds the max lock-free size (4 bytes)}} | ||
| } |
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