[SelectionDAG] Make SelectionDAG aware of the known bits in USUBO and…

… SSUBO and SUBC.

Summary:
Depends on D30379

This improves the state of things for the sub class of operation.

Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D30436

llvm-svn: 297482

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -2297,8 +2297,6 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
     KnownOne &= KnownOne2;
     KnownZero &= KnownZero2;
     break;
-  case ISD::SSUBO:
-  case ISD::USUBO:
   case ISD::SMULO:
   case ISD::UMULO:
     if (Op.getResNo() != 1)
@@ -2493,8 +2491,19 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
     // All bits are zero except the low bit.
     KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1);
     break;
-
-  case ISD::SUB: {
+  case ISD::USUBO:
+  case ISD::SSUBO:
+    if (Op.getResNo() == 1) {
+      // If we know the result of a setcc has the top bits zero, use this info.
+      if (TLI->getBooleanContents(Op.getOperand(0).getValueType()) ==
+              TargetLowering::ZeroOrOneBooleanContent &&
+          BitWidth > 1)
+        KnownZero.setBits(1, BitWidth);
+      break;
+    }
+    LLVM_FALLTHROUGH;
+  case ISD::SUB:
+  case ISD::SUBC: {
     if (ConstantSDNode *CLHS = isConstOrConstSplat(Op.getOperand(0))) {
       // We know that the top bits of C-X are clear if X contains less bits
       // than C (i.e. no wrap-around can happen).  For example, 20-X is

llvm/test/CodeGen/X86/known-bits.ll

@@ -247,11 +247,11 @@ define {i32, i1} @knownbits_usubo_ssubo(i64 %a0, i64 %a1) nounwind {
 ; X64:       # BB#0:
 ; X64-NEXT:    shlq $32, %rdi
 ; X64-NEXT:    shlq $32, %rsi
-; X64-NEXT:    subq %rsi, %rdi
-; X64-NEXT:    setb %cl
+; X64-NEXT:    cmpq %rsi, %rdi
+; X64-NEXT:    setb %al
 ; X64-NEXT:    seto %dl
-; X64-NEXT:    leal (%rdi,%rdi), %eax
-; X64-NEXT:    orb %cl, %dl
+; X64-NEXT:    orb %al, %dl
+; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    retq
   %1 = shl i64 %a0, 32
   %2 = shl i64 %a1, 32