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[AMDGPU] Pattern for v_xor3_b32
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This also allows three op patterns to use increased constant bus
limit of GFX10.

Differential Revision: https://reviews.llvm.org/D61763

llvm-svn: 360395
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@rampitec
rampitec committed May 10, 2019
1 parent 4fa4df9 commit 6419685
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Showing 9 changed files with 405 additions and 1 deletion.
5 changes: 4 additions & 1 deletion llvm/lib/Target/AMDGPU/VOP3Instructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -560,7 +560,9 @@ class ThreeOpFrag<SDPatternOperator op1, SDPatternOperator op2> : PatFrag<
if (!Operands[i]->isDivergent() &&
!isInlineImmediate(Operands[i].getNode())) {
ConstantBusUses++;
if (ConstantBusUses >= 2)
// This uses AMDGPU::V_ADD3_U32, but all three operand instructions
// have the same constant bus limit.
if (ConstantBusUses > Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32))
return false;
}
}
Expand Down Expand Up @@ -625,6 +627,7 @@ def : ThreeOp_i32_Pats<xor, add, V_XAD_U32>;

let SubtargetPredicate = isGFX10Plus in {
def V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
def : ThreeOp_i32_Pats<xor, xor, V_XOR3_B32>;
} // End SubtargetPredicate = isGFX10Plus

//===----------------------------------------------------------------------===//
Expand Down
53 changes: 53 additions & 0 deletions llvm/test/CodeGen/AMDGPU/add3.ll
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s

; ===================================================================================
; V_ADD3_U32
Expand All @@ -17,6 +18,11 @@ define amdgpu_ps float @add3(i32 %a, i32 %b, i32 %c) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: add3:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2
; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, %b
%result = add i32 %x, %c
%bc = bitcast i32 %result to float
Expand All @@ -36,6 +42,12 @@ define amdgpu_ps float @mad_no_add3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
; GFX9-NEXT: v_mad_u32_u24 v0, v0, v1, v4
; GFX9-NEXT: v_mad_u32_u24 v0, v2, v3, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: mad_no_add3:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mad_u32_u24 v0, v0, v1, v4
; GFX10-NEXT: v_mad_u32_u24 v0, v2, v3, v0
; GFX10-NEXT: ; return to shader part epilog
%a0 = shl i32 %a, 8
%a1 = lshr i32 %a0, 8
%b0 = shl i32 %b, 8
Expand Down Expand Up @@ -69,6 +81,11 @@ define amdgpu_ps float @add3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
; GFX9-NEXT: s_add_i32 s3, s3, s2
; GFX9-NEXT: v_add_u32_e32 v0, s3, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: add3_vgpr_b:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_add3_u32 v0, s3, s2, v0
; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, %b
%result = add i32 %x, %c
%bc = bitcast i32 %result to float
Expand All @@ -86,6 +103,11 @@ define amdgpu_ps float @add3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_add3_u32 v0, v1, v2, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: add3_vgpr_all2:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_add3_u32 v0, v1, v2, v0
; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %b, %c
%result = add i32 %a, %x
%bc = bitcast i32 %result to float
Expand All @@ -103,6 +125,11 @@ define amdgpu_ps float @add3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_add3_u32 v0, s2, v0, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: add3_vgpr_bc:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_add3_u32 v0, s2, v0, v1
; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, %b
%result = add i32 %x, %c
%bc = bitcast i32 %result to float
Expand All @@ -120,6 +147,11 @@ define amdgpu_ps float @add3_vgpr_const(i32 %a, i32 %b) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_add3_u32 v0, v0, v1, 16
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: add3_vgpr_const:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_add3_u32 v0, v0, v1, 16
; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, %b
%result = add i32 %x, 16
%bc = bitcast i32 %result to float
Expand All @@ -139,6 +171,12 @@ define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x
; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: add3_multiuse_outer:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2
; GFX10-NEXT: v_mul_lo_u32 v1, v0, v3
; GFX10-NEXT: ; return to shader part epilog
%inner = add i32 %a, %b
%outer = add i32 %inner, %c
%x1 = mul i32 %outer, %x
Expand All @@ -160,6 +198,12 @@ define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_add_u32_e32 v1, v0, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: add3_multiuse_inner:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_add_nc_u32_e32 v1, v0, v2
; GFX10-NEXT: ; return to shader part epilog
%inner = add i32 %a, %b
%outer = add i32 %inner, %c
%r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
Expand Down Expand Up @@ -190,6 +234,15 @@ define amdgpu_ps float @add3_uniform_vgpr(float inreg %a, float inreg %b, float
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: add3_uniform_vgpr:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_add_f32_e64 v1, s3, 2.0
; GFX10-NEXT: v_add_f32_e64 v2, s2, 1.0
; GFX10-NEXT: v_add_f32_e64 v0, 0x40400000, s4
; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v1, v0
; GFX10-NEXT: ; return to shader part epilog
%a1 = fadd float %a, 1.0
%b2 = fadd float %b, 2.0
%c3 = fadd float %c, 3.0
Expand Down
31 changes: 31 additions & 0 deletions llvm/test/CodeGen/AMDGPU/add_shl.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s

; ===================================================================================
; V_ADD_LSHL_U32
Expand All @@ -17,6 +18,11 @@ define amdgpu_ps float @add_shl(i32 %a, i32 %b, i32 %c) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: add_shl:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, v2
; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, %b
%result = shl i32 %x, %c
%bc = bitcast i32 %result to float
Expand All @@ -35,6 +41,11 @@ define amdgpu_ps float @add_shl_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {
; GFX9-NEXT: s_add_i32 s2, s2, s3
; GFX9-NEXT: v_lshlrev_b32_e64 v0, v0, s2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: add_shl_vgpr_c:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_add_lshl_u32 v0, s2, s3, v0
; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, %b
%result = shl i32 %x, %c
%bc = bitcast i32 %result to float
Expand All @@ -52,6 +63,11 @@ define amdgpu_ps float @add_shl_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_add_lshl_u32 v0, v0, s2, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: add_shl_vgpr_ac:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_add_lshl_u32 v0, v0, s2, v1
; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, %b
%result = shl i32 %x, %c
%bc = bitcast i32 %result to float
Expand All @@ -69,6 +85,11 @@ define amdgpu_ps float @add_shl_vgpr_const(i32 %a, i32 %b) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, 9
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: add_shl_vgpr_const:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, 9
; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, %b
%result = shl i32 %x, 9
%bc = bitcast i32 %result to float
Expand All @@ -87,6 +108,11 @@ define amdgpu_ps float @add_shl_vgpr_const_inline_const(i32 %a) {
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7e800
; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: add_shl_vgpr_const_inline_const:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x7e800
; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, 1012
%result = shl i32 %x, 9
%bc = bitcast i32 %result to float
Expand All @@ -108,6 +134,11 @@ define amdgpu_ps float @add_shl_vgpr_inline_const_x2(i32 %a) {
; GFX9-NEXT: v_mov_b32_e32 v1, 0x600
; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: add_shl_vgpr_inline_const_x2:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x600
; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, 3
%result = shl i32 %x, 9
%bc = bitcast i32 %result to float
Expand Down
31 changes: 31 additions & 0 deletions llvm/test/CodeGen/AMDGPU/and_or.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s

; ===================================================================================
; V_AND_OR_B32
Expand All @@ -17,6 +18,11 @@ define amdgpu_ps float @and_or(i32 %a, i32 %b, i32 %c) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_or_b32 v0, v0, v1, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: and_or:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_or_b32 v0, v0, v1, v2
; GFX10-NEXT: ; return to shader part epilog
%x = and i32 %a, %b
%result = or i32 %x, %c
%bc = bitcast i32 %result to float
Expand All @@ -36,6 +42,11 @@ define amdgpu_ps float @and_or_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
; GFX9-NEXT: v_and_b32_e32 v0, s2, v0
; GFX9-NEXT: v_or_b32_e32 v0, s3, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_b:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_or_b32 v0, s2, v0, s3
; GFX10-NEXT: ; return to shader part epilog
%x = and i32 %a, %b
%result = or i32 %x, %c
%bc = bitcast i32 %result to float
Expand All @@ -53,6 +64,11 @@ define amdgpu_ps float @and_or_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_or_b32 v0, v0, v1, s2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_ab:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_or_b32 v0, v0, v1, s2
; GFX10-NEXT: ; return to shader part epilog
%x = and i32 %a, %b
%result = or i32 %x, %c
%bc = bitcast i32 %result to float
Expand All @@ -70,6 +86,11 @@ define amdgpu_ps float @and_or_vgpr_const(i32 %a, i32 %b) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_or_b32 v0, v0, 4, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_const:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_or_b32 v0, v0, 4, v1
; GFX10-NEXT: ; return to shader part epilog
%x = and i32 4, %a
%result = or i32 %x, %b
%bc = bitcast i32 %result to float
Expand All @@ -88,6 +109,11 @@ define amdgpu_ps float @and_or_vgpr_const_inline_const(i32 %a) {
; GFX9-NEXT: v_mov_b32_e32 v1, 0x808
; GFX9-NEXT: v_and_or_b32 v0, v0, 20, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_const_inline_const:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_or_b32 v0, v0, 20, 0x808
; GFX10-NEXT: ; return to shader part epilog
%x = and i32 20, %a
%result = or i32 %x, 2056
%bc = bitcast i32 %result to float
Expand All @@ -105,6 +131,11 @@ define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_or_b32 v0, v0, 4, 1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_inline_const_x2:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_or_b32 v0, v0, 4, 1
; GFX10-NEXT: ; return to shader part epilog
%x = and i32 4, %a
%result = or i32 %x, 1
%bc = bitcast i32 %result to float
Expand Down
26 changes: 26 additions & 0 deletions llvm/test/CodeGen/AMDGPU/or3.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s

; ===================================================================================
; V_OR3_B32
Expand All @@ -17,6 +18,11 @@ define amdgpu_ps float @or3(i32 %a, i32 %b, i32 %c) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: or3:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX10-NEXT: ; return to shader part epilog
%x = or i32 %a, %b
%result = or i32 %x, %c
%bc = bitcast i32 %result to float
Expand All @@ -37,6 +43,11 @@ define amdgpu_ps float @or3_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) {
; GFX9-NEXT: v_or_b32_e32 v0, s2, v0
; GFX9-NEXT: v_or_b32_e32 v0, s3, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: or3_vgpr_a:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_or3_b32 v0, v0, s2, s3
; GFX10-NEXT: ; return to shader part epilog
%x = or i32 %a, %b
%result = or i32 %x, %c
%bc = bitcast i32 %result to float
Expand All @@ -54,6 +65,11 @@ define amdgpu_ps float @or3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: or3_vgpr_all2:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0
; GFX10-NEXT: ; return to shader part epilog
%x = or i32 %b, %c
%result = or i32 %a, %x
%bc = bitcast i32 %result to float
Expand All @@ -71,6 +87,11 @@ define amdgpu_ps float @or3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_or3_b32 v0, s2, v0, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: or3_vgpr_bc:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_or3_b32 v0, s2, v0, v1
; GFX10-NEXT: ; return to shader part epilog
%x = or i32 %a, %b
%result = or i32 %x, %c
%bc = bitcast i32 %result to float
Expand All @@ -88,6 +109,11 @@ define amdgpu_ps float @or3_vgpr_const(i32 %a, i32 %b) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_or3_b32 v0, v1, v0, 64
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: or3_vgpr_const:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_or3_b32 v0, v1, v0, 64
; GFX10-NEXT: ; return to shader part epilog
%x = or i32 64, %b
%result = or i32 %x, %a
%bc = bitcast i32 %result to float
Expand Down
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