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[GlobalISel] Handle div-by-pow2 (#83155)
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This patch adds similar handling of div-by-pow2 as in `SelectionDAG`.
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@shiltian
shiltian committed Mar 29, 2024
1 parent 2f05b89 commit 661bb9d
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Showing 7 changed files with 2,504 additions and 741 deletions.
8 changes: 8 additions & 0 deletions llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
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Original file line number Diff line number Diff line change
Expand Up @@ -673,6 +673,14 @@ class CombinerHelper {
bool matchSDivByConst(MachineInstr &MI);
void applySDivByConst(MachineInstr &MI);

/// Given an G_SDIV \p MI expressing a signed divided by a pow2 constant,
/// return expressions that implements it by shifting.
bool matchDivByPow2(MachineInstr &MI, bool IsSigned);
void applySDivByPow2(MachineInstr &MI);
/// Given an G_UDIV \p MI expressing an unsigned divided by a pow2 constant,
/// return expressions that implements it by shifting.
void applyUDivByPow2(MachineInstr &MI);

// G_UMULH x, (1 << c)) -> x >> (bitwidth - c)
bool matchUMulHToLShr(MachineInstr &MI);
void applyUMulHToLShr(MachineInstr &MI);
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16 changes: 15 additions & 1 deletion llvm/include/llvm/Target/GlobalISel/Combine.td
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Expand Up @@ -179,6 +179,7 @@ def FmArcp : MIFlagEnum<"FmArcp">;
def FmContract : MIFlagEnum<"FmContract">;
def FmAfn : MIFlagEnum<"FmAfn">;
def FmReassoc : MIFlagEnum<"FmReassoc">;
def IsExact : MIFlagEnum<"IsExact">;

def MIFlags;
// def not; -> Already defined as a SDNode
Expand Down Expand Up @@ -1036,7 +1037,20 @@ def sdiv_by_const : GICombineRule<
[{ return Helper.matchSDivByConst(*${root}); }]),
(apply [{ Helper.applySDivByConst(*${root}); }])>;

def intdiv_combines : GICombineGroup<[udiv_by_const, sdiv_by_const]>;
def sdiv_by_pow2 : GICombineRule<
(defs root:$root),
(match (G_SDIV $dst, $x, $y, (MIFlags (not IsExact))):$root,
[{ return Helper.matchDivByPow2(*${root}, /*IsSigned=*/true); }]),
(apply [{ Helper.applySDivByPow2(*${root}); }])>;

def udiv_by_pow2 : GICombineRule<
(defs root:$root),
(match (G_UDIV $dst, $x, $y, (MIFlags (not IsExact))):$root,
[{ return Helper.matchDivByPow2(*${root}, /*IsSigned=*/false); }]),
(apply [{ Helper.applyUDivByPow2(*${root}); }])>;

def intdiv_combines : GICombineGroup<[udiv_by_const, sdiv_by_const,
sdiv_by_pow2, udiv_by_pow2]>;

def reassoc_ptradd : GICombineRule<
(defs root:$root, build_fn_matchinfo:$matchinfo),
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91 changes: 91 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5270,6 +5270,97 @@ MachineInstr *CombinerHelper::buildSDivUsingMul(MachineInstr &MI) {
return MIB.buildMul(Ty, Res, Factor);
}

bool CombinerHelper::matchDivByPow2(MachineInstr &MI, bool IsSigned) {
assert((MI.getOpcode() == TargetOpcode::G_SDIV ||
MI.getOpcode() == TargetOpcode::G_UDIV) &&
"Expected SDIV or UDIV");
auto &Div = cast<GenericMachineInstr>(MI);
Register RHS = Div.getReg(2);
auto MatchPow2 = [&](const Constant *C) {
auto *CI = dyn_cast<ConstantInt>(C);
return CI && (CI->getValue().isPowerOf2() ||
(IsSigned && CI->getValue().isNegatedPowerOf2()));
};
return matchUnaryPredicate(MRI, RHS, MatchPow2, /*AllowUndefs=*/false);
}

void CombinerHelper::applySDivByPow2(MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::G_SDIV && "Expected SDIV");
auto &SDiv = cast<GenericMachineInstr>(MI);
Register Dst = SDiv.getReg(0);
Register LHS = SDiv.getReg(1);
Register RHS = SDiv.getReg(2);
LLT Ty = MRI.getType(Dst);
LLT ShiftAmtTy = getTargetLowering().getPreferredShiftAmountTy(Ty);
LLT CCVT =
Ty.isVector() ? LLT::vector(Ty.getElementCount(), 1) : LLT::scalar(1);

Builder.setInstrAndDebugLoc(MI);

// Effectively we want to lower G_SDIV %lhs, %rhs, where %rhs is a power of 2,
// to the following version:
//
// %c1 = G_CTTZ %rhs
// %inexact = G_SUB $bitwidth, %c1
// %sign = %G_ASHR %lhs, $(bitwidth - 1)
// %lshr = G_LSHR %sign, %inexact
// %add = G_ADD %lhs, %lshr
// %ashr = G_ASHR %add, %c1
// %ashr = G_SELECT, %isoneorallones, %lhs, %ashr
// %zero = G_CONSTANT $0
// %neg = G_NEG %ashr
// %isneg = G_ICMP SLT %rhs, %zero
// %res = G_SELECT %isneg, %neg, %ashr

unsigned BitWidth = Ty.getScalarSizeInBits();
auto Zero = Builder.buildConstant(Ty, 0);

auto Bits = Builder.buildConstant(ShiftAmtTy, BitWidth);
auto C1 = Builder.buildCTTZ(ShiftAmtTy, RHS);
auto Inexact = Builder.buildSub(ShiftAmtTy, Bits, C1);
// Splat the sign bit into the register
auto Sign = Builder.buildAShr(
Ty, LHS, Builder.buildConstant(ShiftAmtTy, BitWidth - 1));

// Add (LHS < 0) ? abs2 - 1 : 0;
auto LSrl = Builder.buildLShr(Ty, Sign, Inexact);
auto Add = Builder.buildAdd(Ty, LHS, LSrl);
auto AShr = Builder.buildAShr(Ty, Add, C1);

// Special case: (sdiv X, 1) -> X
// Special Case: (sdiv X, -1) -> 0-X
auto One = Builder.buildConstant(Ty, 1);
auto MinusOne = Builder.buildConstant(Ty, -1);
auto IsOne = Builder.buildICmp(CmpInst::Predicate::ICMP_EQ, CCVT, RHS, One);
auto IsMinusOne =
Builder.buildICmp(CmpInst::Predicate::ICMP_EQ, CCVT, RHS, MinusOne);
auto IsOneOrMinusOne = Builder.buildOr(CCVT, IsOne, IsMinusOne);
AShr = Builder.buildSelect(Ty, IsOneOrMinusOne, LHS, AShr);

// If divided by a positive value, we're done. Otherwise, the result must be
// negated.
auto Neg = Builder.buildNeg(Ty, AShr);
auto IsNeg = Builder.buildICmp(CmpInst::Predicate::ICMP_SLT, CCVT, RHS, Zero);
Builder.buildSelect(MI.getOperand(0).getReg(), IsNeg, Neg, AShr);
MI.eraseFromParent();
}

void CombinerHelper::applyUDivByPow2(MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::G_UDIV && "Expected UDIV");
auto &UDiv = cast<GenericMachineInstr>(MI);
Register Dst = UDiv.getReg(0);
Register LHS = UDiv.getReg(1);
Register RHS = UDiv.getReg(2);
LLT Ty = MRI.getType(Dst);
LLT ShiftAmtTy = getTargetLowering().getPreferredShiftAmountTy(Ty);

Builder.setInstrAndDebugLoc(MI);

auto C1 = Builder.buildCTTZ(ShiftAmtTy, RHS);
Builder.buildLShr(MI.getOperand(0).getReg(), LHS, C1);
MI.eraseFromParent();
}

bool CombinerHelper::matchUMulHToLShr(MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::G_UMULH);
Register RHS = MI.getOperand(2).getReg();
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41 changes: 12 additions & 29 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
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Expand Up @@ -670,36 +670,19 @@ define amdgpu_kernel void @bfe_sext_in_reg_i24(ptr addrspace(1) %out, ptr addrsp
define amdgpu_kernel void @simplify_demanded_bfe_sdiv(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
; GFX6-LABEL: simplify_demanded_bfe_sdiv:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, 2.0
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: v_mul_lo_u32 v1, v0, -2
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x100001
; GFX6-NEXT: s_ashr_i32 s2, s0, 31
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: s_add_i32 s0, s0, s2
; GFX6-NEXT: s_xor_b32 s0, s0, s2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 1, v0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 2, v1
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_subrev_i32_e64 v2, s[0:1], 2, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 2, v1
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_load_dword s3, s[2:3], 0x0
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_bfe_i32 s3, s3, 0x100001
; GFX6-NEXT: s_ashr_i32 s4, s3, 31
; GFX6-NEXT: s_lshr_b32 s4, s4, 31
; GFX6-NEXT: s_add_i32 s3, s3, s4
; GFX6-NEXT: s_ashr_i32 s3, s3, 1
; GFX6-NEXT: v_mov_b32_e32 v0, s3
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
%src = load i32, ptr addrspace(1) %in, align 4
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %src, i32 1, i32 16)
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147 changes: 35 additions & 112 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -279,125 +279,27 @@ define i32 @v_sdiv_i32_pow2k_denom(i32 %num) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, 0x45800000
; CHECK-NEXT: v_mov_b32_e32 v3, 0xfffff000
; CHECK-NEXT: v_mov_b32_e32 v4, 0x1000
; CHECK-NEXT: v_lshrrev_b32_e32 v1, 20, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_mul_lo_u32 v3, v2, v3
; CHECK-NEXT: v_mul_hi_u32 v3, v2, v3
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2
; CHECK-NEXT: v_lshlrev_b32_e32 v3, 12, v2
; CHECK-NEXT: v_add_i32_e32 v5, vcc, 1, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v4
; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[4:5]
; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, 0x1000, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[4:5]
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v2
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_ashrrev_i32_e32 v0, 12, v0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i32 %num, 4096
ret i32 %result
}

define <2 x i32> @v_sdiv_v2i32_pow2k_denom(<2 x i32> %num) {
; GISEL-LABEL: v_sdiv_v2i32_pow2k_denom:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v0
; GISEL-NEXT: v_mov_b32_e32 v3, 0x1000
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, 0x1000
; GISEL-NEXT: v_mov_b32_e32 v5, 0xfffff000
; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v6
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v2
; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
; GISEL-NEXT: v_mul_lo_u32 v5, v4, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v4, v5
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v0, v4
; GISEL-NEXT: v_mul_hi_u32 v4, v1, v4
; GISEL-NEXT: v_lshlrev_b32_e32 v7, 12, v5
; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v5
; GISEL-NEXT: v_lshlrev_b32_e32 v9, 12, v4
; GISEL-NEXT: v_add_i32_e32 v10, vcc, 1, v4
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v9
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3
; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v0, v3
; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v1, v3
; GISEL-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[6:7]
; GISEL-NEXT: v_subrev_i32_e32 v8, vcc, 0x1000, v1
; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v7, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v5
; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[6:7]
; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
; GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
; GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v8, vcc
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v2
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_sdiv_v2i32_pow2k_denom:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v0
; CGP-NEXT: v_rcp_iflag_f32_e32 v3, 0x45800000
; CGP-NEXT: v_mov_b32_e32 v4, 0xfffff000
; CGP-NEXT: v_mov_b32_e32 v5, 0x1000
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CGP-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v6
; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v3, v3
; CGP-NEXT: v_xor_b32_e32 v1, v1, v6
; CGP-NEXT: v_mul_lo_u32 v4, v3, v4
; CGP-NEXT: v_mul_hi_u32 v4, v3, v4
; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; CGP-NEXT: v_mul_hi_u32 v4, v0, v3
; CGP-NEXT: v_mul_hi_u32 v3, v1, v3
; CGP-NEXT: v_lshlrev_b32_e32 v7, 12, v4
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; CGP-NEXT: v_lshlrev_b32_e32 v9, 12, v3
; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v3
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v9
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v5
; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v8, s[4:5]
; CGP-NEXT: v_sub_i32_e32 v7, vcc, v0, v5
; CGP-NEXT: v_cmp_ge_u32_e64 s[6:7], v1, v5
; CGP-NEXT: v_cndmask_b32_e64 v3, v3, v10, s[6:7]
; CGP-NEXT: v_subrev_i32_e32 v8, vcc, 0x1000, v1
; CGP-NEXT: v_cndmask_b32_e64 v0, v0, v7, s[4:5]
; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v4
; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[6:7]
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v3
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
; CGP-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
; CGP-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
; CGP-NEXT: v_xor_b32_e32 v1, v1, v6
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
; CGP-NEXT: s_setpc_b64 s[30:31]
; CHECK-LABEL: v_sdiv_v2i32_pow2k_denom:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v0
; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; CHECK-NEXT: v_lshrrev_b32_e32 v2, 20, v2
; CHECK-NEXT: v_lshrrev_b32_e32 v3, 20, v3
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; CHECK-NEXT: v_ashrrev_i32_e32 v0, 12, v0
; CHECK-NEXT: v_ashrrev_i32_e32 v1, 12, v1
; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = sdiv <2 x i32> %num, <i32 4096, i32 4096>
ret <2 x i32> %result
}
Expand Down Expand Up @@ -884,3 +786,24 @@ define <2 x i32> @v_sdiv_v2i32_24bit(<2 x i32> %num, <2 x i32> %den) {
%result = sdiv <2 x i32> %num.mask, %den.mask
ret <2 x i32> %result
}

define i32 @v_sdiv_i32_exact(i32 %num) {
; CHECK-LABEL: v_sdiv_i32_exact:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_ashrrev_i32_e32 v0, 12, v0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = sdiv exact i32 %num, 4096
ret i32 %result
}

define <2 x i32> @v_sdiv_v2i32_exact(<2 x i32> %num) {
; CHECK-LABEL: v_sdiv_v2i32_exact:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_ashrrev_i32_e32 v0, 12, v0
; CHECK-NEXT: v_ashrrev_i32_e32 v1, 10, v1
; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = sdiv exact <2 x i32> %num, <i32 4096, i32 1024>
ret <2 x i32> %result
}
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