[AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instruction

This adds a new variant of the DC system instruction for persistent memory. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52480 llvm-svn: 343216
llvm · Sep 27, 2018 · 6930b12 · 6930b12
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commit 6930b12
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Showing 8 changed files with 27 additions and 2 deletions.
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
@@ -217,6 +217,9 @@ def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
 def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true",
   "Enable execution and data prediction invalidation instructions" >;
 
+def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
+    "true", "Enable Cache Clean to Point of Deep Persistence" >;
+
 //===----------------------------------------------------------------------===//
 // Architectures.
 //
@@ -236,7 +239,7 @@ def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
 def HasV8_5aOps : SubtargetFeature<
   "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
   [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecCtrl,
-   FeaturePredCtrl]
+   FeaturePredCtrl, FeatureCacheDeepPersist]
 >;
 
 //===----------------------------------------------------------------------===//

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -70,6 +70,8 @@ def HasSpecCtrl      : Predicate<"Subtarget->hasSpecCtrl()">,
                        AssemblerPredicate<"FeatureSpecCtrl", "specctrl">;
 def HasPredCtrl      : Predicate<"Subtarget->hasPredCtrl()">,
                        AssemblerPredicate<"FeaturePredCtrl", "predctrl">;
+def HasCCDP          : Predicate<"Subtarget->hasCCDP()">,
+                       AssemblerPredicate<"FeatureCacheDeepPersist", "ccdp">;
 def IsLE             : Predicate<"Subtarget->isLittleEndian()">;
 def IsBE             : Predicate<"!Subtarget->isLittleEndian()">;
 def UseAlternateSExtLoadCVTF32

diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -99,6 +99,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
   bool HasFRInt3264 = false;
   bool HasSpecCtrl = false;
   bool HasPredCtrl = false;
+  bool HasCCDP = false;
 
   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
   bool HasZeroCycleRegMove = false;
@@ -316,6 +317,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
   bool hasFRInt3264() const { return HasFRInt3264; }
   bool hasSpecCtrl() { return HasSpecCtrl; }
   bool hasPredCtrl() { return HasPredCtrl; }
+  bool hasCCDP() { return HasCCDP; }
 
   bool isLittleEndian() const { return IsLittle; }
 

diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -105,6 +105,9 @@ def : DC<"CISW",  0b000, 0b0111, 0b1110, 0b010>;
 let Requires = [{ {AArch64::HasV8_2aOps} }] in
 def : DC<"CVAP",  0b011, 0b0111, 0b1100, 0b001>;
 
+let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in
+def : DC<"CVADP",  0b011, 0b0111, 0b1101, 0b001>;
+
 //===----------------------------------------------------------------------===//
 // IC (instruction cache maintenance) instruction options.
 //===----------------------------------------------------------------------===//

diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2757,6 +2757,7 @@ static const struct Extension {
   { "ras", {AArch64::FeatureRAS} },
   { "lse", {AArch64::FeatureLSE} },
   { "predctrl", {AArch64::FeaturePredCtrl} },
+  { "ccdp", {AArch64::FeatureCacheDeepPersist} },
 
   // FIXME: Unsupported extensions
   { "pan", {} },

diff --git a/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
@@ -812,7 +812,7 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
     }
     break;
     // DC aliases
-    case 4: case 6: case 10: case 11: case 12: case 14:
+    case 4: case 6: case 10: case 11: case 12: case 13: case 14:
     {
       const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
       if (!DC || !DC->haveFeatures(STI.getFeatureBits()))

diff --git a/llvm/test/MC/AArch64/armv8.5a-persistent-memory.s b/llvm/test/MC/AArch64/armv8.5a-persistent-memory.s
@@ -0,0 +1,7 @@
+// RUN:     llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ccdp  < %s      | FileCheck %s
+// RUN:     llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s      | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-ccdp  < %s 2>&1 | FileCheck %s --check-prefix=NOCCDP
+
+dc cvadp, x7
+// CHECK:  dc cvadp, x7   // encoding: [0x27,0x7d,0x0b,0xd5]
+// NOCCDP: error: DC CVADP requires ccdp
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-persistent-memory.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-persistent-memory.txt
@@ -0,0 +1,7 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+ccdp  --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.5a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-ccdp  --disassemble < %s | FileCheck %s --check-prefix=NOCCDP
+
+[0x27,0x7d,0x0b,0xd5]
+# CHECK:  dc cvadp, x7
+# NOCCDP: sys #3, c7, c13, #1, x7