AArch64: Set shift bit of TLSLE HI12 add instruction

Summary: AArch64 LLVM assembler emits add instruction without shift bit to calculate the higher 12-bit address of TLS variables in local exec model.  This generates wrong code sequence to access TLS variables with thread offset larger than 0x1000.

Reviewers: t.p.northover, peter.smith, rovka

Subscribers: salim.nasser, aemerson, llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D24702

llvm-svn: 282057

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

@@ -263,6 +263,12 @@ AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
 
   ++MCNumFixups;
 
+  // Set the shift bit of the add instruction for relocation types
+  // R_AARCH64_TLSLE_ADD_TPREL_HI12 and R_AARCH64_TLSLD_ADD_DTPREL_HI12.
+  AArch64MCExpr::VariantKind RefKind = cast<AArch64MCExpr>(Expr)->getKind();
+  if (RefKind == AArch64MCExpr::VK_TPREL_HI12 ||
+      RefKind == AArch64MCExpr::VK_DTPREL_HI12)
+    ShiftVal = 12;
   return ShiftVal == 0 ? 0 : (1 << ShiftVal);
 }
 

llvm/test/MC/AArch64/tls-add-shift.s

@@ -0,0 +1,12 @@
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj < %s -o - | \
+// RUN:   llvm-objdump -r -d - | FileCheck %s
+
+	// TLS add TPREL
+	add x2, x1, #:tprel_hi12:var
+// CHECK: add x2, x1, #0, lsl #12
+// CHECK-NEXT: R_AARCH64_TLSLE_ADD_TPREL_HI12 var
+
+	// TLS add DTPREL
+	add x4, x3, #:dtprel_hi12:var
+// CHECK: add x4, x3, #0, lsl #12
+// CHECK-NEXT: R_AARCH64_TLSLD_ADD_DTPREL_HI12 var