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[RISCV] Add scheduling information for SiFive VCIX (#86093)
This adds `RISCVScheduleXSf.td` with `SchedWrite` definitions for all VCIX instructions and uses it in `RISCVSchedSiFive7.td` to set default latencies for these instructions, helping with issue #83391. Of course these default latencies cannot be accurate (since each coprocessor will have different latencies), but this seems to be enough to avoid some of the problematic behavior described in the bug. In any case, this seems to be enough to help with #83391 in our internal testing. A subsequent discussion is how to structure the code such that it's easier for downstream consumers of this to use `SiFive7` scheduling model with accurate VCIX latencies. But we can probably have a separate issue to discuss that.
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//===-- RISCVScheduleXSf.td - Scheduling Definitions XSf ---*- tablegen -*-===// | ||
// | ||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
// See https://llvm.org/LICENSE.txt for license information. | ||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
// | ||
//===----------------------------------------------------------------------===// | ||
// | ||
// This file describes the scheduling information for SiFive extensions. | ||
// | ||
//===----------------------------------------------------------------------===// | ||
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multiclass LMULSchedWritesVCIX<string id>{ | ||
defm "" : LMULSchedWrites<"WriteVC_" # id>; | ||
defm "" : LMULSchedWrites<"WriteVC_V_" # id>; | ||
} | ||
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defm "" : LMULSchedWritesVCIX<"I">; | ||
defm "" : LMULSchedWritesVCIX<"X">; | ||
defm "" : LMULSchedWritesVCIX<"IV">; | ||
defm "" : LMULSchedWritesVCIX<"VV">; | ||
defm "" : LMULSchedWritesVCIX<"XV">; | ||
defm "" : LMULSchedWritesVCIX<"IVV">; | ||
defm "" : LMULSchedWritesVCIX<"IVW">; | ||
defm "" : LMULSchedWritesVCIX<"VVV">; | ||
defm "" : LMULSchedWritesVCIX<"VVW">; | ||
defm "" : LMULSchedWritesVCIX<"XVV">; | ||
defm "" : LMULSchedWritesVCIX<"XVW">; | ||
foreach f = ["FPR16", "FPR32", "FPR64"] in { | ||
defm "" : LMULSchedWritesVCIX<f # "V">; | ||
defm "" : LMULSchedWritesVCIX<f # "VV">; | ||
defm "" : LMULSchedWritesVCIX<f # "VW">; | ||
} | ||
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multiclass LMULWriteResVCIX<string id, list<ProcResourceKind> resources>{ | ||
defm : LMULWriteRes<"WriteVC_" # id, resources>; | ||
defm : LMULWriteRes<"WriteVC_V_" # id, resources>; | ||
} | ||
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multiclass UnsupportedSchedXsfvcp { | ||
let Unsupported = true in { | ||
defm : LMULWriteResVCIX<"I", []>; | ||
defm : LMULWriteResVCIX<"X", []>; | ||
defm : LMULWriteResVCIX<"IV", []>; | ||
defm : LMULWriteResVCIX<"VV", []>; | ||
defm : LMULWriteResVCIX<"XV", []>; | ||
defm : LMULWriteResVCIX<"IVV", []>; | ||
defm : LMULWriteResVCIX<"IVW", []>; | ||
defm : LMULWriteResVCIX<"VVV", []>; | ||
defm : LMULWriteResVCIX<"VVW", []>; | ||
defm : LMULWriteResVCIX<"XVV", []>; | ||
defm : LMULWriteResVCIX<"XVW", []>; | ||
foreach f = ["FPR16", "FPR32", "FPR64"] in { | ||
defm : LMULWriteResVCIX<f # "V", []>; | ||
defm : LMULWriteResVCIX<f # "VV", []>; | ||
defm : LMULWriteResVCIX<f # "VW", []>; | ||
} | ||
} | ||
} |