[MachineCombiner] Preserve debug instruction number

Each target's `TargetInstrInfo` is responsible for announcing which code
patterns it is able to transform during the MachineCombiner pass.
Currently, these patterns are applied without preserving the debug
instruction number required by the InstrRef implementation of
LiveDebugValues. As such, we've seen a number of examples where debug
information is dropped for variables in InstrRef mode that were
otherwise available in VarLoc mode. This has been observed both in X86
and AArch examples.

This commit is an initial attempt at preserving said numbers by changing
the general (target agnostic) implementation of TargetInstrInfo: the
reassociation pattern must keep the debug number of the "top level"
instruction, i.e., the instruction whose value represents the final
value of the arithmetic expression. Intermediate values must have their
debug number dropped, as they have no equivalent value in the
unoptimized code.

Future work is required to update each target's
`TargetInstrInfo::genAlternativeCodeSequence` method.

Differential Revision: https://reviews.llvm.org/D145759

llvm/lib/CodeGen/TargetInstrInfo.cpp

@@ -1017,6 +1017,17 @@ void TargetInstrInfo::reassociateOps(
   InsInstrs.push_back(MIB2);
   DelInstrs.push_back(&Prev);
   DelInstrs.push_back(&Root);
+
+  // We transformed:
+  // B = A op X (Prev)
+  // C = B op Y (Root)
+  // Into:
+  // B = X op Y (MIB1)
+  // C = A op B (MIB2)
+  // C has the same value as before, B doesn't; as such, keep the debug number
+  // of C but not of B.
+  if (unsigned OldRootNum = Root.peekDebugInstrNum())
+    MIB2.getInstr()->setDebugInstrNum(OldRootNum);
 }
 
 void TargetInstrInfo::genAlternativeCodeSequence(

llvm/test/CodeGen/X86/machine-combiner-dbg.mir

@@ -0,0 +1,58 @@
+# RUN: llc -mtriple=x86_64-gnu-linux -run-pass=machine-combiner %s -o - | FileCheck %s
+
+--- |
+  define float @reassoc_me(float %f1, float %f2, float %f3, float %f4) !dbg !4 {
+    %add = fadd reassoc nsz float %f1, %f2, !dbg !10
+    %add1 = fadd reassoc nsz float %add, %f3, !dbg !10
+    %add2 = fadd reassoc nsz float %add1, %f4, !dbg !10
+    call void @llvm.dbg.value(metadata float %add2, metadata !9, metadata !DIExpression()), !dbg !10
+    ret float %add2, !dbg !10
+  }
+
+  declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!2, !3}
+
+  !0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "hello", isOptimized: true, emissionKind: FullDebug)
+  !1 = !DIFile(filename: "reassoc.c", directory: "blah")
+  !2 = !{i32 7, !"Dwarf Version", i32 4}
+  !3 = !{i32 2, !"Debug Info Version", i32 3}
+  !4 = distinct !DISubprogram(name: "reassoc_me", scope: !1, file: !1, line: 1, type: !5, scopeLine: 1, unit: !0, retainedNodes: !8)
+  !5 = !DISubroutineType(types: !6)
+  !6 = !{!7, !7, !7, !7, !7}
+  !7 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float)
+  !8 = !{!9}
+  !9 = !DILocalVariable(name: "temp3", scope: !4, file: !1, line: 4, type: !7)
+  !10 = !DILocation(line: 0, scope: !4)
+
+...
+---
+name:            reassoc_me
+alignment:       16
+debugInstrRef:   true
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $xmm0, $xmm1, $xmm2, $xmm3
+
+    %3:fr32 = COPY $xmm3
+    %2:fr32 = COPY $xmm2
+    %1:fr32 = COPY $xmm1
+    %0:fr32 = COPY $xmm0
+    %4:fr32 = nsz reassoc nofpexcept ADDSSrr %0, %1, implicit $mxcsr, debug-location !10
+    %5:fr32 = nsz reassoc nofpexcept ADDSSrr %4, %2, implicit $mxcsr, debug-location !10
+    %6:fr32 = nsz reassoc nofpexcept ADDSSrr %5, %3, implicit $mxcsr, debug-instr-number 1, debug-location !10
+    DBG_INSTR_REF !9, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !10
+    $xmm0 = COPY %6, debug-location !10
+    RET 0, $xmm0, debug-location !10
+
+  ; CHECK: ![[VAR:.*]] = !DILocalVariable(name: "temp3"
+  ; CHECK:      %[[arg3:.*]]:fr32 = COPY $xmm3
+  ; CHECK-NEXT: %[[arg2:.*]]:fr32 = COPY $xmm2
+  ; CHECK-NEXT: %[[arg1:.*]]:fr32 = COPY $xmm1
+  ; CHECK-NEXT: %[[arg0:.*]]:fr32 = COPY $xmm0
+  ; CHECK-NEXT: %[[add1:.*]]:fr32 = {{.*}} ADDSSrr %[[arg0]], %[[arg1]]
+  ; CHECK-NEXT: %[[add2:.*]]:fr32 = {{.*}} ADDSSrr %[[arg2]], %[[arg3]]
+  ; CHECK-NEXT:                            ADDSSrr %[[add1]], killed %[[add2]], {{.*}} debug-instr-number 1
+  ; CHECK-NEXT: DBG_INSTR_REF ![[VAR]], !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0)
+...