Revert "[DPWBS-1421] Add support for fixup resolution of SBR-form ins…

…truction"

This reverts commit ff10b5d.

This change broke our test pipeline. Since we now accept symbols on scaled 4 operands,
we need to handle all instruction formats with these operands.

llvm/lib/Target/TriCore/AsmParser/TriCoreAsmParser.cpp

@@ -240,13 +240,12 @@ struct TriCoreOperand : public MCParsedAsmOperand {
 
     bool IsConstantImm = evaluateConstantImm(Imm, VK);
 
-    // only allow symbols when the operand is: uimm4_lsb0/simm15_lsb0
-    // /simm24_lsb0 which correspond to _4REL/_15REL/_24REL relocations
+    // only allow symbols when the operand is: simm15_lsb0 or simm24_lsb0
+    // which are corresponds to _15REL and _24REL relocations
     if (!IsConstantImm)
-      IsValid =
-          ((WIDTH == 15 || WIDTH == 24) && SIGNED) || (WIDTH == 4 && !SIGNED)
-              ? TriCoreAsmParser::classifySymbolRef(getImm(), VK, Imm)
-              : false;
+      IsValid = (WIDTH == 15 || WIDTH == 24) && SIGNED
+                    ? TriCoreAsmParser::classifySymbolRef(getImm(), VK, Imm)
+                    : false;
     else
       IsValid = SIGNED ? isShiftedInt<WIDTH, SHIFT>(Imm)
                        : isShiftedUInt<WIDTH, SHIFT>(Imm);
@@ -608,17 +607,10 @@ bool TriCoreAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   auto MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
                                           MissingFeatures, MatchingInlineAsm);
 
-  // RAII to reset 16 and 32 bit code emission flags
-  struct CodeBitsReset {
-    TriCoreAsmParser *p;
-    CodeBitsReset(TriCoreAsmParser *p) : p(p) {}
-    ~CodeBitsReset() {
-      if (!(p->getSTI().getFeatureBits()[TriCore::Only32BitInstructions])) {
-        p->setFeatureBits(TriCore::Allow16BitInstructions, "allow-16bit");
-        p->setFeatureBits(TriCore::Allow32BitInstructions, "allow-32bit");
-      }
-    }
-  } c(this);
+  if (!(getSTI().getFeatureBits()[TriCore::Only32BitInstructions])) {
+    setFeatureBits(TriCore::Allow16BitInstructions, "allow-16bit");
+    setFeatureBits(TriCore::Allow32BitInstructions, "allow-32bit");
+  }
 
   switch (MatchResult) {
   default:

llvm/lib/Target/TriCore/MCTargetDesc/TriCoreAsmBackend.cpp

@@ -41,6 +41,12 @@ class TriCoreAsmBackend : public MCAsmBackend {
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override;
 
+  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
+                            const MCRelaxableFragment *DF,
+                            const MCAsmLayout &Layout) const override {
+    return false;
+  }
+
   unsigned getNumFixupKinds() const override {
     return TriCore::NumTargetFixupKinds;
   }
@@ -58,10 +64,6 @@ class TriCoreAsmBackend : public MCAsmBackend {
         {"fixup_lo2", 16, 16, 0},
         {"fixup_18abs", 12, 20, 0},
         {"fixup_15rel", 16, 15, MCFixupKindInfo::FKF_IsPCRel},
-        {"fixup_4rel", 8, 4,
-         MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_Constant},
-        {"fixup_4rel2", 8, 4,
-         MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_Constant},
     };
 
     static_assert((array_lengthof(Infos)) == TriCore::NumTargetFixupKinds,
@@ -74,71 +76,18 @@ class TriCoreAsmBackend : public MCAsmBackend {
   }
 
   bool mayNeedRelaxation(const MCInst &Inst,
-                         const MCSubtargetInfo &STI) const override;
-  unsigned getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const;
-  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
-                        MCInst &Res) const override;
-  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
-                            const MCRelaxableFragment *DF,
-                            const MCAsmLayout &Layout) const override;
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
-};
-
-unsigned TriCoreAsmBackend::getRelaxedOpcode(unsigned Op,
-                                             const MCSubtargetInfo &STI) const {
-  bool Is32BitAllowed = STI.getFeatureBits()[TriCore::Allow32BitInstructions];
-
-  switch (Op) {
-  default:
-    return Op;
-  case TriCore::JEQ_16_d15dc:
-    return TriCore::JEQ_16_d15dlc;
-  case TriCore::JNE_16_d15dc:
-    return TriCore::JNE_16_d15dlc;
-  case TriCore::JEQ_16_d15dlc:
-    return Is32BitAllowed ? TriCore::JEQ_ddc : Op;
-  case TriCore::JNE_16_d15dlc:
-    return Is32BitAllowed ? TriCore::JNE_ddc : Op;
+                         const MCSubtargetInfo &STI) const override {
+    return false;
   }
-}
 
-bool TriCoreAsmBackend::mayNeedRelaxation(const MCInst &Inst,
-                                          const MCSubtargetInfo &STI) const {
-  if (getRelaxedOpcode(Inst.getOpcode(), STI) != Inst.getOpcode())
-    return true;
-
-  return false;
-}
-
-bool TriCoreAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
-                                             uint64_t Value,
-                                             const MCRelaxableFragment *DF,
-                                             const MCAsmLayout &Layout) const {
-
-  int64_t Offset = int64_t(Value);
+  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
+                        MCInst &Res) const override {
 
-  switch (Fixup.getTargetKind()) {
-  default:
-    return false;
-  case TriCore::fixup_4rel:
-    // Relax if the value is out of the range of uimm4_lsb0's [0,30]
-    return Offset > 30 || Offset < 0;
-  case TriCore::fixup_4rel2:
-    // Relax if the value is out of the range of disp4_16's [32,62]
-    return Offset > 62 || Offset < 32;
+    report_fatal_error("TriCoreAsmBackend::relaxInstruction() unimplemented");
   }
-}
 
-void TriCoreAsmBackend::relaxInstruction(const MCInst &Inst,
-                                         const MCSubtargetInfo &STI,
-                                         MCInst &Res) const {
-  unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI);
-
-  // We don't need to change the operands only we just need to update
-  // to the proper opcode.
-  Res = Inst;
-  Res.setOpcode(RelaxedOp);
-}
+  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+};
 
 bool TriCoreAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
   if ((Count % 2) != 0)
@@ -182,18 +131,6 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
     if (Value & 1)
       Ctx.reportError(Fixup.getLoc(), "fixup must be 2-byte aligned");
     return (Value >> 1) & 0x7fff;
-  case TriCore::fixup_4rel:
-    if (!isUInt<5>(Value))
-      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
-    if (Value & 1)
-      Ctx.reportError(Fixup.getLoc(), "fixup must be 2-byte aligned");
-    return (Value >> 1) & 0x1f;
-  case TriCore::fixup_4rel2:
-    if (Value > 62 || Value < 32)
-      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
-    if (Value & 1)
-      Ctx.reportError(Fixup.getLoc(), "fixup must be 2-byte aligned");
-    return (Value >> 1) - 16;
   }
 }
 

llvm/lib/Target/TriCore/MCTargetDesc/TriCoreELFObjectWriter.cpp

@@ -12,8 +12,6 @@
 #include "llvm/MC/MCFixup.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/Support/ErrorHandling.h"
-#include "llvm/MC/MCValue.h"
-#include "llvm/MC/MCContext.h"
 
 using namespace llvm;
 
@@ -56,8 +54,7 @@ unsigned TriCoreELFObjectWriter::getRelocType(MCContext &Ctx,
   unsigned Kind = Fixup.getTargetKind();
   switch (Kind) {
   default:
-    Ctx.reportFatalError(Fixup.getLoc(), "unsupported relocation on symbol");
-    return ELF::R_TRICORE_NONE;
+    llvm_unreachable("invalid fixup kind!");
   case FK_Data_4:
     return ELF::R_TRICORE_32ABS;
   case TriCore::fixup_24rel:

llvm/lib/Target/TriCore/MCTargetDesc/TriCoreFixupKinds.h

@@ -46,13 +46,6 @@ enum Fixups {
   // 15 bit pc-relative immediate used in BR format (internally multiplied by 2)
   fixup_15rel,
 
-  // 4 bit pc-relative immediate used in SBR format (internally multiplied by 2)
-  fixup_4rel,
-
-  // 4 bit pc-relative immediate used in SBR format (internally add 16
-  // and multiplied by 2)
-  fixup_4rel2,
-
   fixup_invalid,
   // the number of fixups for this target
   NumTargetFixupKinds = fixup_invalid - FirstTargetFixupKind

llvm/lib/Target/TriCore/MCTargetDesc/TriCoreMCCodeEmitter.cpp

@@ -245,18 +245,6 @@ void TriCoreMCCodeEmitter::createFixups(const MCInst &MI, unsigned OpNo,
     case TriCoreII::BRRFrm:
       FixupKind = TriCore::fixup_15rel;
       break;
-
-    case TriCoreII::SBRFrm:
-      switch (OpCode) {
-      default:
-        FixupKind = TriCore::fixup_4rel;
-        break;
-      case TriCore::JEQ_16_d15dlc:
-      case TriCore::JNE_16_d15dlc:
-        FixupKind = TriCore::fixup_4rel2;
-        break;
-      }
-      break;
     }
   }
   assert(FixupKind != TriCore::fixup_invalid && "Unhandled expression!");