Skip to content

Commit

Permalink
[RISCV] Trim RVV isel pats matchable via DAG post-process
Browse files Browse the repository at this point in the history 
In D122512, several masked patterns were added to support lowering of
vector-predicated float-to-int and int-to-float conversions. With the
introduction of these patterns, all of the old "unmasked" patterns are
matchable via the DAG post-process introduced in D118810, once the relevant
opcode entries are set up in the helper table.

Locally this reduces the generated isel table by 4%.

Reviewed By: arcbbb

Differential Revision: https://reviews.llvm.org/D122637
  • Loading branch information
@frasercrmck
frasercrmck committed Mar 30, 2022
1 parent ea043ea commit 7504757
Show file tree
Hide file tree
Showing 2 changed files with 5 additions and 45 deletions.
6 changes: 5 additions & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
View file
Expand Up @@ -2102,6 +2102,7 @@ multiclass PseudoVEXT_VF2 {
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
def "_" # m.MX # "_MASK" :
VPseudoUnaryMaskTA<m.vrclass, m.f2vrclass, constraints>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
}
}
Expand All @@ -2118,6 +2119,7 @@ multiclass PseudoVEXT_VF4 {
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
def "_" # m.MX # "_MASK" :
VPseudoUnaryMaskTA<m.vrclass, m.f4vrclass, constraints>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
}
}
Expand All @@ -2134,6 +2136,7 @@ multiclass PseudoVEXT_VF8 {
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
def "_" # m.MX # "_MASK" :
VPseudoUnaryMaskTA<m.vrclass, m.f8vrclass, constraints>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
}
}
Expand Down Expand Up @@ -2669,7 +2672,8 @@ multiclass VPseudoConversion<VReg RetClass,
def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>;
def "_" # MInfo.MX # "_TU": VPseudoUnaryNoMaskTU<RetClass, Op1Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskTA<RetClass, Op1Class,
Constraint>;
Constraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>;
}
}

Expand Down
44 changes: 0 additions & 44 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
View file
Expand Up @@ -549,10 +549,6 @@ multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix,
foreach vtiTofti = fraction_list in {
defvar vti = vtiTofti.Vti;
defvar fti = vtiTofti.Fti;
def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2),
true_mask, VLOpFrag)),
(!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX)
fti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2),
(fti.Mask V0), VLOpFrag)),
(!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX#"_MASK")
Expand All @@ -565,11 +561,6 @@ multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix,
multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
foreach fvti = AllFloatVectors in {
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask true_mask),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
fvti.RegClass:$rs1, GPR:$vl, ivti.Log2SEW)>;
def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask V0),
VLOpFrag)),
Expand All @@ -582,11 +573,6 @@ multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
multiclass VPatConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> {
foreach fvti = AllFloatVectors in {
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
(ivti.Mask true_mask),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
ivti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
(ivti.Mask V0),
VLOpFrag)),
Expand All @@ -600,11 +586,6 @@ multiclass VPatWConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask true_mask),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
fvti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask V0),
VLOpFrag)),
Expand All @@ -618,11 +599,6 @@ multiclass VPatWConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> {
foreach vtiToWti = AllWidenableIntToFloatVectors in {
defvar ivti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti;
def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
(ivti.Mask true_mask),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
ivti.RegClass:$rs1, GPR:$vl, ivti.Log2SEW)>;
def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
(ivti.Mask V0),
VLOpFrag)),
Expand All @@ -636,11 +612,6 @@ multiclass VPatNConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
foreach vtiToWti = AllWidenableIntToFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti;
def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1),
(fwti.Mask true_mask),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_"#vti.LMul.MX)
fwti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1),
(fwti.Mask V0),
VLOpFrag)),
Expand All @@ -654,11 +625,6 @@ multiclass VPatNConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1),
(iwti.Mask true_mask),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
iwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1),
(iwti.Mask V0),
VLOpFrag)),
Expand Down Expand Up @@ -1547,11 +1513,6 @@ foreach fvti = AllFloatVectors in {
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask true_mask),
VLOpFrag)),
(!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX)
fvti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask V0),
VLOpFrag)),
Expand All @@ -1568,11 +1529,6 @@ foreach fvti = AllFloatVectors in {
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
def : Pat<(fvti.Vector (riscv_fpround_vl (fwti.Vector fwti.RegClass:$rs1),
(fwti.Mask true_mask),
VLOpFrag)),
(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX)
fwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
def : Pat<(fvti.Vector (riscv_fpround_vl (fwti.Vector fwti.RegClass:$rs1),
(fwti.Mask V0),
VLOpFrag)),
Expand Down

0 comments on commit 7504757

Please sign in to comment.