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[LoongArch] Lower BlockAddress/JumpTable
This patch uses a unified interface for lower GlobalAddress ConstantPool BlockAddress and JumpTable. This patch allows lowering addresses by using PC-relative addressing for DSO-local symbols, and accessing the address through the global offset table for DSO-preemptable symbols. Remove hardcoded `MininumJumpTableEntries` for test lower JumpTable. Also updated some test cases using ConstantPool, due to the addition of relocation information. Differential Revision: https://reviews.llvm.org/D134431
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llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
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| Original file line number | Diff line number | Diff line change |
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| //===-- LoongArchExpandPseudoInsts.cpp - Expand pseudo instructions -------===// | ||
| // | ||
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
| // See https://llvm.org/LICENSE.txt for license information. | ||
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
| // | ||
| //===----------------------------------------------------------------------===// | ||
| // | ||
| // This file contains a pass that expands pseudo instructions into target | ||
| // instructions. | ||
| // | ||
| //===----------------------------------------------------------------------===// | ||
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| #include "LoongArch.h" | ||
| #include "LoongArchInstrInfo.h" | ||
| #include "LoongArchTargetMachine.h" | ||
| #include "MCTargetDesc/LoongArchBaseInfo.h" | ||
| #include "MCTargetDesc/LoongArchMCTargetDesc.h" | ||
| #include "llvm/CodeGen/LivePhysRegs.h" | ||
| #include "llvm/CodeGen/MachineFunctionPass.h" | ||
| #include "llvm/CodeGen/MachineInstrBuilder.h" | ||
| #include "llvm/MC/MCContext.h" | ||
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| using namespace llvm; | ||
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| #define LOONGARCH_PRERA_EXPAND_PSEUDO_NAME \ | ||
| "LoongArch Pre-RA pseudo instruction expansion pass" | ||
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| namespace { | ||
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| class LoongArchPreRAExpandPseudo : public MachineFunctionPass { | ||
| public: | ||
| const LoongArchInstrInfo *TII; | ||
| static char ID; | ||
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| LoongArchPreRAExpandPseudo() : MachineFunctionPass(ID) { | ||
| initializeLoongArchPreRAExpandPseudoPass(*PassRegistry::getPassRegistry()); | ||
| } | ||
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| bool runOnMachineFunction(MachineFunction &MF) override; | ||
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| void getAnalysisUsage(AnalysisUsage &AU) const override { | ||
| AU.setPreservesCFG(); | ||
| MachineFunctionPass::getAnalysisUsage(AU); | ||
| } | ||
| StringRef getPassName() const override { | ||
| return LOONGARCH_PRERA_EXPAND_PSEUDO_NAME; | ||
| } | ||
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| private: | ||
| bool expandMBB(MachineBasicBlock &MBB); | ||
| bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, | ||
| MachineBasicBlock::iterator &NextMBBI); | ||
| bool expandPcalau12iInstPair(MachineBasicBlock &MBB, | ||
| MachineBasicBlock::iterator MBBI, | ||
| MachineBasicBlock::iterator &NextMBBI, | ||
| unsigned FlagsHi, unsigned SecondOpcode, | ||
| unsigned FlagsLo); | ||
| bool expandLoadAddressPcrel(MachineBasicBlock &MBB, | ||
| MachineBasicBlock::iterator MBBI, | ||
| MachineBasicBlock::iterator &NextMBBI); | ||
| bool expandLoadAddressGot(MachineBasicBlock &MBB, | ||
| MachineBasicBlock::iterator MBBI, | ||
| MachineBasicBlock::iterator &NextMBBI); | ||
| }; | ||
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| char LoongArchPreRAExpandPseudo::ID = 0; | ||
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| bool LoongArchPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) { | ||
| TII = | ||
| static_cast<const LoongArchInstrInfo *>(MF.getSubtarget().getInstrInfo()); | ||
| bool Modified = false; | ||
| for (auto &MBB : MF) | ||
| Modified |= expandMBB(MBB); | ||
| return Modified; | ||
| } | ||
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| bool LoongArchPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) { | ||
| bool Modified = false; | ||
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| MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); | ||
| while (MBBI != E) { | ||
| MachineBasicBlock::iterator NMBBI = std::next(MBBI); | ||
| Modified |= expandMI(MBB, MBBI, NMBBI); | ||
| MBBI = NMBBI; | ||
| } | ||
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| return Modified; | ||
| } | ||
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| bool LoongArchPreRAExpandPseudo::expandMI( | ||
| MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, | ||
| MachineBasicBlock::iterator &NextMBBI) { | ||
| switch (MBBI->getOpcode()) { | ||
| case LoongArch::PseudoLA_PCREL: | ||
| return expandLoadAddressPcrel(MBB, MBBI, NextMBBI); | ||
| case LoongArch::PseudoLA_GOT: | ||
| return expandLoadAddressGot(MBB, MBBI, NextMBBI); | ||
| } | ||
| return false; | ||
| } | ||
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| bool LoongArchPreRAExpandPseudo::expandPcalau12iInstPair( | ||
| MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, | ||
| MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi, | ||
| unsigned SecondOpcode, unsigned FlagsLo) { | ||
| MachineFunction *MF = MBB.getParent(); | ||
| MachineInstr &MI = *MBBI; | ||
| DebugLoc DL = MI.getDebugLoc(); | ||
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| Register DestReg = MI.getOperand(0).getReg(); | ||
| Register ScratchReg = | ||
| MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass); | ||
| MachineOperand &Symbol = MI.getOperand(1); | ||
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| BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg) | ||
| .addDisp(Symbol, 0, FlagsHi); | ||
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| MachineInstr *SecondMI = | ||
| BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg) | ||
| .addReg(ScratchReg) | ||
| .addDisp(Symbol, 0, FlagsLo); | ||
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| if (MI.hasOneMemOperand()) | ||
| SecondMI->addMemOperand(*MF, *MI.memoperands_begin()); | ||
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| MI.eraseFromParent(); | ||
| return true; | ||
| } | ||
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| bool LoongArchPreRAExpandPseudo::expandLoadAddressPcrel( | ||
| MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, | ||
| MachineBasicBlock::iterator &NextMBBI) { | ||
| MachineFunction *MF = MBB.getParent(); | ||
| const auto &STI = MF->getSubtarget<LoongArchSubtarget>(); | ||
| unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; | ||
| return expandPcalau12iInstPair(MBB, MBBI, NextMBBI, LoongArchII::MO_PCREL_HI, | ||
| SecondOpcode, LoongArchII::MO_PCREL_LO); | ||
| } | ||
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| bool LoongArchPreRAExpandPseudo::expandLoadAddressGot( | ||
| MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, | ||
| MachineBasicBlock::iterator &NextMBBI) { | ||
| MachineFunction *MF = MBB.getParent(); | ||
| const auto &STI = MF->getSubtarget<LoongArchSubtarget>(); | ||
| unsigned SecondOpcode = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W; | ||
| return expandPcalau12iInstPair(MBB, MBBI, NextMBBI, LoongArchII::MO_GOT_PC_HI, | ||
| SecondOpcode, LoongArchII::MO_GOT_PC_LO); | ||
| } | ||
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| } // end namespace | ||
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| INITIALIZE_PASS(LoongArchPreRAExpandPseudo, "LoongArch-prera-expand-pseudo", | ||
| LOONGARCH_PRERA_EXPAND_PSEUDO_NAME, false, false) | ||
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| namespace llvm { | ||
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| FunctionPass *createLoongArchPreRAExpandPseudoPass() { | ||
| return new LoongArchPreRAExpandPseudo(); | ||
| } | ||
|
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| } // end namespace llvm |
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