[DPWBS-1485] feat(InstructionSelector): select G_FREEZE to COPY

Select G_FREEZE to COPY as there is no FREEZE MIR instruction.
This matches the behavior in SelectionDAG and other backends.

add selection tests

llvm/lib/Target/TriCore/TriCoreInstructionSelector.cpp

@@ -92,6 +92,7 @@ class TriCoreInstructionSelector : public InstructionSelector {
   bool selectFPExt(MachineInstr &I, const MachineRegisterInfo &MRI) const;
   bool selectFPTrunc(MachineInstr &I, const MachineRegisterInfo &MRI) const;
   bool selectFrameIndex(MachineInstr &I, const MachineRegisterInfo &MRI) const;
+  bool selectFreeze(MachineInstr &I, MachineRegisterInfo &MRI) const;
   bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI) const;
   bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI) const;
   bool selectICmp(MachineInstr &I, const MachineRegisterInfo &MRI) const;
@@ -521,6 +522,8 @@ bool TriCoreInstructionSelector::select(MachineInstr &I) {
     return selectFPTrunc(I, MRI);
   case TargetOpcode::G_FRAME_INDEX:
     return selectFrameIndex(I, MRI);
+  case TargetOpcode::G_FREEZE:
+    return selectFreeze(I, MRI);
   case TargetOpcode::G_GLOBAL_VALUE:
     return selectGlobalValue(I, MRI);
   case TargetOpcode::G_ICMP:
@@ -1546,6 +1549,28 @@ bool TriCoreInstructionSelector::selectFrameIndex(
   return true;
 }
 
+bool TriCoreInstructionSelector::selectFreeze(MachineInstr &I,
+                                              MachineRegisterInfo &MRI) const {
+
+  assert(I.getOpcode() == TargetOpcode::G_FREEZE);
+
+  const Register DstReg = I.getOperand(0).getReg();
+  const LLT DstTy = MRI.getType(DstReg);
+  const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
+  const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB);
+
+  if (!DstRC) {
+    LLVM_DEBUG(
+        dbgs() << "Unable to determine TargetRegisterClass for G_FREEZE\n");
+    return false;
+  }
+
+  TriCoreRegisterBankInfo::constrainGenericRegister(DstReg, *DstRC, MRI);
+  I.setDesc(TII.get(TargetOpcode::COPY));
+
+  return true;
+}
+
 bool TriCoreInstructionSelector::selectFltRounds(
     MachineInstr &I, MachineRegisterInfo &MRI) const {
   Register DstReg = I.getOperand(0).getReg();

llvm/test/CodeGen/TriCore/GlobalIsel/select-freeze.mir

@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=tricore -global-isel -run-pass=instruction-select \
+# RUN:   -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            test_freeze_p0
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: addrregbank }
+  - { id: 1, class: addrregbank }
+body: |
+  bb.0:
+    liveins: $a4
+    ; CHECK-LABEL: name: test_freeze_p0
+    ; CHECK: [[COPY:%[0-9]+]]:addrregs = COPY $a4
+    ; CHECK: $a2 = COPY [[COPY]]
+    %0(p0) = COPY $a4
+    %1(p0) = G_FREEZE %0
+    $a2 = COPY %1(p0)
+...
+
+---
+name:            test_freeze_s32
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: dataregbank }
+  - { id: 1, class: dataregbank }
+body: |
+  bb.0:
+    liveins: $d4
+    ; CHECK-LABEL: name: test_freeze_s32
+    ; CHECK: [[COPY:%[0-9]+]]:dataregs = COPY $d4
+    ; CHECK: $d2 = COPY [[COPY]]
+    %0(s32) = COPY $d4
+    %1(s32) = G_FREEZE %0
+    $d2 = COPY %1(s32)
+...
+
+---
+name:            test_freeze_s64
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: dataregbank }
+  - { id: 1, class: dataregbank }
+body: |
+  bb.0:
+    liveins: $e4
+    ; CHECK-LABEL: name: test_freeze_s64
+    ; CHECK: [[COPY:%[0-9]+]]:extdataregs = COPY $e4
+    ; CHECK: $e2 = COPY [[COPY]]
+    %0(s64) = COPY $e4
+    %1(s64) = G_FREEZE %0
+    $e2 = COPY %1(s64)
+...