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Revert "[SPARC] Mark the %g0 register as constant & use it to materia…
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…lize zeros"

2 of the Sparc tests are now failing.

This reverts commit 2c41310.
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@brad0
brad0 committed Dec 7, 2022
1 parent 258bb45 commit 7806f86
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Showing 17 changed files with 304 additions and 301 deletions.
4 changes: 0 additions & 4 deletions llvm/lib/Target/Sparc/SparcInstr64Bit.td
View file
Expand Up @@ -60,10 +60,6 @@ defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, shift_imm6, I64Regs>;

// Single-instruction patterns.

// Zero immediate.
def : Pat<(i64 0), (COPY (i64 G0))>,
Requires<[Is64Bit]>;

// The ALU instructions want their simm13 operands as i32 immediates.
def as_i32imm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
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12 changes: 2 additions & 10 deletions llvm/lib/Target/Sparc/SparcInstrInfo.td
View file
Expand Up @@ -1767,7 +1767,8 @@ let Predicates = [HasV9] in {
//===----------------------------------------------------------------------===//

// Zero immediate.
def : Pat<(i32 0), (COPY (i32 G0))>;
def : Pat<(i32 0),
(ORrr (i32 G0), (i32 G0))>;
// Small immediates.
def : Pat<(i32 simm13:$val),
(ORri (i32 G0), imm:$val)>;
Expand Down Expand Up @@ -1848,15 +1849,6 @@ def : Pat<(atomic_store_16 ADDRri:$dst, i32:$val), (STHri ADDRri:$dst, $val)>;
def : Pat<(atomic_store_32 ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
def : Pat<(atomic_store_32 ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;

// Zero register pair.
// This forces zeroing of the upper half to be done with ORrr instead of COPY,
// since there `COPY G0` will be converted into `COPY G0_G1` later on, which
// is not what we want in this case.
def : Pat<(build_vector (i32 0), (i32 0)),
(INSERT_SUBREG (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
(ORrr (i32 G0), (i32 G0)), sub_even),
(i32 G0), sub_odd)>;

// extract_vector
def : Pat<(extractelt (v2i32 IntPair:$Rn), 0),
(i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>;
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5 changes: 1 addition & 4 deletions llvm/lib/Target/Sparc/SparcRegisterInfo.td
View file
Expand Up @@ -126,9 +126,7 @@ def OTHERWIN : SparcCtrlReg<13, "OTHERWIN">;
def WSTATE : SparcCtrlReg<14, "WSTATE">;

// Integer registers
def G0 : Ri< 0, "G0">, DwarfRegNum<[0]> {
let isConstant = true;
}
def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
Expand Down Expand Up @@ -380,4 +378,3 @@ let isAllocatable = 0 in {
def PRRegs : RegisterClass<"SP", [i64], 64,
(add TPC, TNPC, TSTATE, TT, TICK, TBA, PSTATE, TL, PIL, CWP,
CANSAVE, CANRESTORE, CLEANWIN, OTHERWIN, WSTATE)>;

4 changes: 2 additions & 2 deletions llvm/test/CodeGen/SPARC/64bit.ll
View file
Expand Up @@ -40,11 +40,11 @@ define i64 @sra_reg(i64 %a, i64 %b) {
; restore %g0, %g0, %o0
;
; CHECK: ret_imm0
; CHECK: mov %g0, %i0
; CHECK: mov 0, %i0

; OPT: ret_imm0
; OPT: retl
; OPT: mov %g0, %o0
; OPT: mov 0, %o0
define i64 @ret_imm0() {
ret i64 0
}
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/SPARC/64cond.ll
View file
Expand Up @@ -112,9 +112,9 @@ entry:
}

; CHECK-LABEL: setcc_resultty
; CHECK-DAG: mov %g0, %o0
; CHECK-DAG: mov 0, %o0
; CHECK-DAG: mov %i0, %o1
; CHECK-DAG: mov %g0, %o2
; CHECK-DAG: mov %o0, %o2
; CHECK-DAG: mov 32, %o3
; CHECK-DAG: call __multi3
; CHECK: cmp
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86 changes: 46 additions & 40 deletions llvm/test/CodeGen/SPARC/atomics.ll
View file
Expand Up @@ -87,24 +87,25 @@ entry:
; SPARC: sll %o4, %o1, %o4
; SPARC: and %o0, 255, %o0
; SPARC: sll %o0, %o1, %o0
; SPARC: andn %g2, %o5, %o5
; SPARC: andn %g2, %o5, %g2
; SPARC: mov %g0, %o5
; SPARC: [[LABEL1:\.L.*]]:
; SPARC: or %o5, %o4, %g2
; SPARC: or %o5, %o0, %g3
; SPARC: cas [%o2], %g3, %g2
; SPARC: mov %g0, %g4
; SPARC: cmp %g2, %g3
; SPARC: or %g2, %o4, %g3
; SPARC: or %g2, %o0, %g4
; SPARC: cas [%o2], %g4, %g3
; SPARC: cmp %g3, %g4
; SPARC: mov %o5, %g4
; SPARC: move %icc, 1, %g4
; SPARC: cmp %g4, 0
; SPARC: bne %icc, [[LABEL2:\.L.*]]
; SPARC: nop
; SPARC: and %g2, %o3, %g3
; SPARC: cmp %o5, %g3
; SPARC: and %g3, %o3, %g4
; SPARC: cmp %g2, %g4
; SPARC: bne %icc, [[LABEL1]]
; SPARC: mov %g3, %o5
; SPARC: mov %g4, %g2
; SPARC: [[LABEL2]]:
; SPARC: retl
; SPARC: srl %g2, %o1, %o0
; SPARC: srl %g3, %o1, %o0
; SPARC64-LABEL: test_cmpxchg_i8
; SPARC64: and %o1, -4, %o2
; SPARC64: mov 3, %o3
Expand All @@ -118,24 +119,25 @@ entry:
; SPARC64: sll %o4, %o1, %o4
; SPARC64: and %o0, 255, %o0
; SPARC64: sll %o0, %o1, %o0
; SPARC64: andn %g2, %o5, %o5
; SPARC64: andn %g2, %o5, %g2
; SPARC64: mov %g0, %o5
; SPARC64: [[LABEL1:\.L.*]]:
; SPARC64: or %o5, %o4, %g2
; SPARC64: or %o5, %o0, %g3
; SPARC64: cas [%o2], %g3, %g2
; SPARC64: mov %g0, %g4
; SPARC64: cmp %g2, %g3
; SPARC64: or %g2, %o4, %g3
; SPARC64: or %g2, %o0, %g4
; SPARC64: cas [%o2], %g4, %g3
; SPARC64: cmp %g3, %g4
; SPARC64: mov %o5, %g4
; SPARC64: move %icc, 1, %g4
; SPARC64: cmp %g4, 0
; SPARC64: bne %icc, [[LABEL2:\.L.*]]
; SPARC64: nop
; SPARC64: and %g2, %o3, %g3
; SPARC64: cmp %o5, %g3
; SPARC64: and %g3, %o3, %g4
; SPARC64: cmp %g2, %g4
; SPARC64: bne %icc, [[LABEL1]]
; SPARC64: mov %g3, %o5
; SPARC64: mov %g4, %g2
; SPARC64: [[LABEL2]]:
; SPARC64: retl
; SPARC64: srl %g2, %o1, %o0
; SPARC64: srl %g3, %o1, %o0
define i8 @test_cmpxchg_i8(i8 %a, i8* %ptr) {
entry:
%pair = cmpxchg i8* %ptr, i8 %a, i8 123 monotonic monotonic
Expand All @@ -158,24 +160,25 @@ entry:
; SPARC: mov 123, %o0
; SPARC: sll %o0, %o1, %o0
; SPARC: sll %o4, %o1, %o4
; SPARC: andn %g2, %o5, %o5
; SPARC: andn %g2, %o5, %g2
; SPARC: mov %g0, %o5
; SPARC: [[LABEL1:\.L.*]]:
; SPARC: or %o5, %o0, %g2
; SPARC: or %o5, %o4, %g3
; SPARC: cas [%o2], %g3, %g2
; SPARC: mov %g0, %g4
; SPARC: cmp %g2, %g3
; SPARC: or %g2, %o0, %g3
; SPARC: or %g2, %o4, %g4
; SPARC: cas [%o2], %g4, %g3
; SPARC: cmp %g3, %g4
; SPARC: mov %o5, %g4
; SPARC: move %icc, 1, %g4
; SPARC: cmp %g4, 0
; SPARC: bne %icc, [[LABEL2:\.L.*]]
; SPARC: nop
; SPARC: and %g2, %o3, %g3
; SPARC: cmp %o5, %g3
; SPARC: and %g3, %o3, %g4
; SPARC: cmp %g2, %g4
; SPARC: bne %icc, [[LABEL1]]
; SPARC: mov %g3, %o5
; SPARC: mov %g4, %g2
; SPARC: [[LABEL2]]:
; SPARC: retl
; SPARC: srl %g2, %o1, %o0
; SPARC: srl %g3, %o1, %o0
; SPARC64: and %o1, -4, %o2
; SPARC64: and %o1, 3, %o1
; SPARC64: xor %o1, 2, %o1
Expand All @@ -189,24 +192,25 @@ entry:
; SPARC64: mov 123, %o0
; SPARC64: sll %o0, %o1, %o0
; SPARC64: sll %o4, %o1, %o4
; SPARC64: andn %g2, %o5, %o5
; SPARC64: andn %g2, %o5, %g2
; SPARC64: mov %g0, %o5
; SPARC64: [[LABEL1:\.L.*]]:
; SPARC64: or %o5, %o0, %g2
; SPARC64: or %o5, %o4, %g3
; SPARC64: cas [%o2], %g3, %g2
; SPARC64: mov %g0, %g4
; SPARC64: cmp %g2, %g3
; SPARC64: or %g2, %o0, %g3
; SPARC64: or %g2, %o4, %g4
; SPARC64: cas [%o2], %g4, %g3
; SPARC64: cmp %g3, %g4
; SPARC64: mov %o5, %g4
; SPARC64: move %icc, 1, %g4
; SPARC64: cmp %g4, 0
; SPARC64: bne %icc, [[LABEL2:\.L.*]]
; SPARC64: nop
; SPARC64: and %g2, %o3, %g3
; SPARC64: cmp %o5, %g3
; SPARC64: and %g3, %o3, %g4
; SPARC64: cmp %g2, %g4
; SPARC64: bne %icc, [[LABEL1]]
; SPARC64: mov %g3, %o5
; SPARC64: mov %g4, %g2
; SPARC64: [[LABEL2]]:
; SPARC64: retl
; SPARC64: srl %g2, %o1, %o0
; SPARC64: srl %g3, %o1, %o0
define i16 @test_cmpxchg_i16(i16 %a, i16* %ptr) {
entry:
%pair = cmpxchg i16* %ptr, i16 %a, i16 123 monotonic monotonic
Expand Down Expand Up @@ -301,12 +305,14 @@ entry:

; SPARC-LABEL: test_load_add_i32
; SPARC: membar
; SPARC: mov %g0
; SPARC: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
; SPARC: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
; SPARC: cas [%o0], [[V]], [[V2]]
; SPARC: membar
; SPARC64-LABEL: test_load_add_i32
; SPARC64: membar
; SPARC64: mov %g0
; SPARC64: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
; SPARC64: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
; SPARC64: cas [%o0], [[V]], [[V2]]
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/SPARC/bigreturn.ll
View file
Expand Up @@ -137,7 +137,7 @@ define { i64, i64 } @ret_i64_pair(i32 %a0, i32 %a1, i64* %p, i64* %q) {
; SPARC-NEXT: .cfi_register %o7, %i7
; SPARC-NEXT: mov %g0, %i4
; SPARC-NEXT: ldd [%i2], %i0
; SPARC-NEXT: mov %g0, %i5
; SPARC-NEXT: mov %i4, %i5
; SPARC-NEXT: std %i4, [%i2]
; SPARC-NEXT: ldd [%i3], %i2
; SPARC-NEXT: restore
Expand Down
40 changes: 21 additions & 19 deletions llvm/test/CodeGen/SPARC/cttz.ll
View file
Expand Up @@ -5,7 +5,8 @@ define i32 @f(i32 %x) {
; CHECK-LABEL: f:
; CHECK: .cfi_startproc
; CHECK-NEXT: ! %bb.0: ! %entry
; CHECK-NEXT: sub %g0, %o0, %o1
; CHECK-NEXT: mov %g0, %o1
; CHECK-NEXT: sub %o1, %o0, %o1
; CHECK-NEXT: and %o0, %o1, %o1
; CHECK-NEXT: sethi 122669, %o2
; CHECK-NEXT: or %o2, 305, %o2
Expand All @@ -31,29 +32,30 @@ define i64 @g(i64 %x) {
; CHECK-LABEL: g:
; CHECK: .cfi_startproc
; CHECK-NEXT: ! %bb.0: ! %entry
; CHECK-NEXT: sub %g0, %o1, %o2
; CHECK-NEXT: and %o1, %o2, %o2
; CHECK-NEXT: sethi 122669, %o3
; CHECK-NEXT: or %o3, 305, %o3
; CHECK-NEXT: smul %o2, %o3, %o2
; CHECK-NEXT: sethi %hi(.LCPI1_0), %o4
; CHECK-NEXT: add %o4, %lo(.LCPI1_0), %o4
; CHECK-NEXT: sub %g0, %o0, %o5
; CHECK-NEXT: and %o0, %o5, %o5
; CHECK-NEXT: smul %o5, %o3, %o3
; CHECK-NEXT: mov %g0, %o2
; CHECK-NEXT: sub %o2, %o1, %o3
; CHECK-NEXT: and %o1, %o3, %o3
; CHECK-NEXT: sethi 122669, %o4
; CHECK-NEXT: or %o4, 305, %o4
; CHECK-NEXT: smul %o3, %o4, %o3
; CHECK-NEXT: sethi %hi(.LCPI1_0), %o5
; CHECK-NEXT: add %o5, %lo(.LCPI1_0), %o5
; CHECK-NEXT: sub %o2, %o0, %g2
; CHECK-NEXT: and %o0, %g2, %g2
; CHECK-NEXT: smul %g2, %o4, %o4
; CHECK-NEXT: srl %o4, 27, %o4
; CHECK-NEXT: ldub [%o5+%o4], %o4
; CHECK-NEXT: srl %o3, 27, %o3
; CHECK-NEXT: ldub [%o4+%o3], %o3
; CHECK-NEXT: srl %o2, 27, %o2
; CHECK-NEXT: ldub [%o4+%o2], %o4
; CHECK-NEXT: add %o3, 32, %o2
; CHECK-NEXT: ldub [%o5+%o3], %o5
; CHECK-NEXT: add %o4, 32, %o3
; CHECK-NEXT: cmp %o1, 0
; CHECK-NEXT: movne %icc, %o4, %o2
; CHECK-NEXT: movne %icc, %o5, %o3
; CHECK-NEXT: or %o1, %o0, %o0
; CHECK-NEXT: cmp %o0, 0
; CHECK-NEXT: move %icc, 0, %o2
; CHECK-NEXT: mov %g0, %o0
; CHECK-NEXT: move %icc, 0, %o3
; CHECK-NEXT: mov %o2, %o0
; CHECK-NEXT: retl
; CHECK-NEXT: mov %o2, %o1
; CHECK-NEXT: mov %o3, %o1
entry:
%0 = call i64 @llvm.cttz.i64(i64 %x, i1 true)
%1 = icmp eq i64 %x, 0
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/SPARC/float-constants.ll
View file
Expand Up @@ -8,7 +8,7 @@
; CHECK: sethi 1049856, %o0
; CHECK: mov %g0, %o1
; CHECK-LE: mov %g0, %o0
; CHECK-LE: sethi 1049856, %o2
; CHECK-LE: sethi 1049856, %o1
define <2 x i32> @bitcast() {
%1 = bitcast double 5.0 to <2 x i32>
ret <2 x i32> %1
Expand All @@ -20,8 +20,8 @@ define <2 x i32> @bitcast() {
; CHECK-LABEL: test_call
; CHECK: sethi 1049856, %o0
; CHECK: mov %g0, %o1
; CHECK-LE: sethi 1049856, %o1
; CHECK-LE: mov %g0, %o0
; CHECK-LE: sethi 1049856, %o1
declare void @a(double)
define void @test_call() {
call void @a(double 5.0)
Expand All @@ -37,9 +37,9 @@ define void @test_call() {
; CHECK: sethi 1048576, %o0
; CHECK: mov %g0, %o1
; CHECK: mov %o0, %o2
; CHECK: mov %g0, %o3
; CHECK-LE: sethi 1048576, %o1
; CHECK: mov %o1, %o3
; CHECK-LE: mov %g0, %o0
; CHECK-LE: sethi 1048576, %o1
declare double @llvm.pow.f64(double, double)
define double @test_intrins_call() {
%1 = call double @llvm.pow.f64(double 2.0, double 2.0)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/SPARC/fshl.ll
View file
Expand Up @@ -31,7 +31,7 @@ define i32 @PR47303() {
; CHECK: .cfi_startproc
; CHECK-NEXT: ! %bb.0: ! %bb
; CHECK-NEXT: retl
; CHECK-NEXT: mov %g0, %o0
; CHECK-NEXT: mov 0, %o0
bb:
%i = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> undef, <4 x i64> undef, <4 x i64> <i64 57, i64 27, i64 12, i64 33>)
%i1 = add <4 x i64> %i, zeroinitializer
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/SPARC/inlineasm.ll
View file
Expand Up @@ -84,8 +84,8 @@ attributes #0 = { "frame-pointer"="all" }

;; Ensures that tied in and out gets allocated properly.
; CHECK-LABEL: test_i64_inout:
; CHECK: mov 5, %i3
; CHECK: mov %g0, %i2
; CHECK: mov 5, %i3
; CHECK: xor %i2, %g0, %i2
; CHECK: mov %i2, %i0
; CHECK: ret
Expand Down
3 changes: 2 additions & 1 deletion llvm/test/CodeGen/SPARC/missinglabel.ll
View file
Expand Up @@ -13,7 +13,8 @@ define void @f(i64 %a0) align 2 {
; CHECK-NEXT: nop
; CHECK-NEXT: ! %bb.1: ! %cond.false
; CHECK-NEXT: .LBB0_2: ! %targetblock
; CHECK-NEXT: cmp %g0, 0
; CHECK-NEXT: mov %g0, %o0
; CHECK-NEXT: cmp %o0, 0
; CHECK-NEXT: bne %icc, .LBB0_4
; CHECK-NEXT: nop
; CHECK-NEXT: ! %bb.3: ! %cond.false.i83
Expand Down

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