[AArch64][SVE] Asm: Support for contiguous, non-faulting LDNF1 (scala…

…r+imm) load instructions

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45684

llvm-svn: 330583

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

@@ -56,6 +56,24 @@ let Predicates = [HasSVE] in {
   defm LD1SB_H : sve_mem_cld_ss<0b1110, "ld1sb", Z_h, ZPR16, GPR64NoXZRshifted8>;
   defm LD1D    : sve_mem_cld_ss<0b1111, "ld1d",  Z_d, ZPR64, GPR64NoXZRshifted64>;
 
+  // non-faulting continuous load with reg+immediate
+  defm LDNF1B_IMM    : sve_mem_cldnf_si<0b0000, "ldnf1b",  Z_b, ZPR8>;
+  defm LDNF1B_H_IMM  : sve_mem_cldnf_si<0b0001, "ldnf1b",  Z_h, ZPR16>;
+  defm LDNF1B_S_IMM  : sve_mem_cldnf_si<0b0010, "ldnf1b",  Z_s, ZPR32>;
+  defm LDNF1B_D_IMM  : sve_mem_cldnf_si<0b0011, "ldnf1b",  Z_d, ZPR64>;
+  defm LDNF1SW_D_IMM : sve_mem_cldnf_si<0b0100, "ldnf1sw", Z_d, ZPR64>;
+  defm LDNF1H_IMM    : sve_mem_cldnf_si<0b0101, "ldnf1h",  Z_h, ZPR16>;
+  defm LDNF1H_S_IMM  : sve_mem_cldnf_si<0b0110, "ldnf1h",  Z_s, ZPR32>;
+  defm LDNF1H_D_IMM  : sve_mem_cldnf_si<0b0111, "ldnf1h",  Z_d, ZPR64>;
+  defm LDNF1SH_D_IMM : sve_mem_cldnf_si<0b1000, "ldnf1sh", Z_d, ZPR64>;
+  defm LDNF1SH_S_IMM : sve_mem_cldnf_si<0b1001, "ldnf1sh", Z_s, ZPR32>;
+  defm LDNF1W_IMM    : sve_mem_cldnf_si<0b1010, "ldnf1w",  Z_s, ZPR32>;
+  defm LDNF1W_D_IMM  : sve_mem_cldnf_si<0b1011, "ldnf1w",  Z_d, ZPR64>;
+  defm LDNF1SB_D_IMM : sve_mem_cldnf_si<0b1100, "ldnf1sb", Z_d, ZPR64>;
+  defm LDNF1SB_S_IMM : sve_mem_cldnf_si<0b1101, "ldnf1sb", Z_s, ZPR32>;
+  defm LDNF1SB_H_IMM : sve_mem_cldnf_si<0b1110, "ldnf1sb", Z_h, ZPR16>;
+  defm LDNF1D_IMM    : sve_mem_cldnf_si<0b1111, "ldnf1d",  Z_d, ZPR64>;
+
   // LD(2|3|4) structured loads with reg+immediate
   defm LD2B_IMM : sve_mem_eld_si<0b00, 0b01, ZZ_b,   "ld2b", simm4Scale2MulVl>;
   defm LD3B_IMM : sve_mem_eld_si<0b00, 0b10, ZZZ_b,  "ld3b", simm4Scale3MulVl>;

llvm/lib/Target/AArch64/SVEInstrFormats.td

@@ -712,6 +712,10 @@ multiclass sve_mem_cld_ss<bits<4> dtype, string asm, RegisterOperand listty,
 }
 
 
+multiclass sve_mem_cldnf_si<bits<4> dtype, string asm, RegisterOperand listty,
+                            ZPRRegOp zprty>
+: sve_mem_cld_si_base<dtype, 1, asm, listty, zprty>;
+
 class sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                      string asm, Operand immtype>
 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4),

llvm/test/MC/AArch64/SVE/ldnf1b-diagnostics.s

@@ -0,0 +1,87 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ldnf1b z23.b, p0/z, [x13, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z23.b, p0/z, [x13, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z29.b, p0/z, [x3, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z29.b, p0/z, [x3, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ldnf1b z27.b, p8/z, [x29, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1b z27.b, p8/z, [x29, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1b z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1b z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1b z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ldnf1b { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ldnf1b { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1b { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/ldnf1b.s

@@ -0,0 +1,104 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ldnf1b     z0.b, p0/z, [x0]
+// CHECK-INST: ldnf1b     { z0.b }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x10,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 10 a4 <unknown>
+
+ldnf1b     z0.h, p0/z, [x0]
+// CHECK-INST: ldnf1b     { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x30,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 30 a4 <unknown>
+
+ldnf1b     z0.s, p0/z, [x0]
+// CHECK-INST: ldnf1b     { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x50,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 50 a4 <unknown>
+
+ldnf1b     z0.d, p0/z, [x0]
+// CHECK-INST: ldnf1b     { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x70,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 70 a4 <unknown>
+
+ldnf1b    { z0.b }, p0/z, [x0]
+// CHECK-INST: ldnf1b    { z0.b }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x10,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 10 a4 <unknown>
+
+ldnf1b    { z0.h }, p0/z, [x0]
+// CHECK-INST: ldnf1b    { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x30,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 30 a4 <unknown>
+
+ldnf1b    { z0.s }, p0/z, [x0]
+// CHECK-INST: ldnf1b    { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x50,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 50 a4 <unknown>
+
+ldnf1b    { z0.d }, p0/z, [x0]
+// CHECK-INST: ldnf1b    { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x70,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 70 a4 <unknown>
+
+ldnf1b    { z31.b }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1b    { z31.b }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x1f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 1f a4 <unknown>
+
+ldnf1b    { z21.b }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1b    { z21.b }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x15,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 15 a4 <unknown>
+
+ldnf1b    { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1b    { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x3f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 3f a4 <unknown>
+
+ldnf1b    { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1b    { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x35,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 35 a4 <unknown>
+
+ldnf1b    { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1b    { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x5f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 5f a4 <unknown>
+
+ldnf1b    { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1b    { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x55,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 55 a4 <unknown>
+
+ldnf1b    { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1b    { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x7f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 7f a4 <unknown>
+
+ldnf1b    { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1b    { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x75,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 75 a4 <unknown>

llvm/test/MC/AArch64/SVE/ldnf1d-diagnostics.s

@@ -0,0 +1,42 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ldnf1d z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1d z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1d z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1d z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ldnf1d z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1d z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ldnf1d { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ldnf1d { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/ldnf1d.s

@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ldnf1d     z0.d, p0/z, [x0]
+// CHECK-INST: ldnf1d     { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xf0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 f0 a5 <unknown>
+
+ldnf1d    { z0.d }, p0/z, [x0]
+// CHECK-INST: ldnf1d    { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xf0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 f0 a5 <unknown>
+
+ldnf1d    { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1d    { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xff,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf ff a5 <unknown>
+
+ldnf1d    { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1d    { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xf5,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 f5 a5 <unknown>

llvm/test/MC/AArch64/SVE/ldnf1h-diagnostics.s

@@ -0,0 +1,72 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ldnf1h z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1h z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1h z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1h z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1h z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1h z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1h z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ldnf1h z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1h z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1h z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1h z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ldnf1h { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ldnf1h { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1h { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: