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[AArch64][MC] Merge FeaturePMU into FeaturePerfMon
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FeaturePMU was created in AArch64 to accommodate one missing system
register, PMMIR_EL1, in commit ffcd769.

However, the Performance Monitors extension already had a target
feature, which is called FeaturePerfMon. Therefore, FeaturePMU is
redundant.

This patch removes FeaturePMU and merges its contents into
FeaturePerfMon.

Reviewed By: dnsampaio

Differential Revision: https://reviews.llvm.org/D109246
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@vhscampos
vhscampos committed Sep 6, 2021
1 parent 93c3e76 commit 79f9c79
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Showing 8 changed files with 10 additions and 45 deletions.
6 changes: 1 addition & 5 deletions llvm/lib/Target/AArch64/AArch64.td
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Expand Up @@ -309,10 +309,6 @@ def FeatureSEL2 : SubtargetFeature<
"sel2", "HasSEL2", "true",
"Enable v8.4-A Secure Exception Level 2 extension">;

def FeaturePMU : SubtargetFeature<
"pmu", "HasPMU", "true",
"Enable v8.4-A PMU extension">;

def FeatureTLB_RMI : SubtargetFeature<
"tlb-rmi", "HasTLB_RMI", "true",
"Enable v8.4-A TLB Range and Maintenance Instructions">;
Expand Down Expand Up @@ -462,7 +458,7 @@ def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
"Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
FeatureNV, FeatureMPAM, FeatureDIT,
FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI,
FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,
FeatureFlagM, FeatureRCPC_IMMO]>;

def HasV8_5aOps : SubtargetFeature<
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3 changes: 0 additions & 3 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Expand Up @@ -63,9 +63,6 @@ def HasAM : Predicate<"Subtarget->hasAM()">,
def HasSEL2 : Predicate<"Subtarget->hasSEL2()">,
AssemblerPredicate<(all_of FeatureSEL2), "sel2">;

def HasPMU : Predicate<"Subtarget->hasPMU()">,
AssemblerPredicate<(all_of FeaturePMU), "pmu">;

def HasTLB_RMI : Predicate<"Subtarget->hasTLB_RMI()">,
AssemblerPredicate<(all_of FeatureTLB_RMI), "tlb-rmi">;

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2 changes: 0 additions & 2 deletions llvm/lib/Target/AArch64/AArch64Subtarget.h
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Expand Up @@ -139,7 +139,6 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
bool HasTRACEV8_4 = false;
bool HasAM = false;
bool HasSEL2 = false;
bool HasPMU = false;
bool HasTLB_RMI = false;
bool HasFlagM = false;
bool HasRCPC_IMMO = false;
Expand Down Expand Up @@ -543,7 +542,6 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
bool hasHCX() const { return HasHCX; }
bool hasLS64() const { return HasLS64; }
bool hasSEL2() const { return HasSEL2; }
bool hasPMU() const { return HasPMU; }
bool hasTLB_RMI() const { return HasTLB_RMI; }
bool hasFlagM() const { return HasFlagM; }
bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
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7 changes: 1 addition & 6 deletions llvm/lib/Target/AArch64/AArch64SystemOperands.td
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Expand Up @@ -970,6 +970,7 @@ def : RWSysReg<"PMUSERENR_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b000>;
def : RWSysReg<"PMINTENSET_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b001>;
def : RWSysReg<"PMINTENCLR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b010>;
def : RWSysReg<"PMOVSSET_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b011>;
def : RWSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>;
def : RWSysReg<"MAIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b000>;
def : RWSysReg<"MAIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b000>;
def : RWSysReg<"MAIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b000>;
Expand Down Expand Up @@ -1411,12 +1412,6 @@ def : RWSysReg<"CNTHPS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b001>;
def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>;
} // FeatureSEL2

// v8.4a PMU registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeaturePMU} }] in {
def : RWSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>;
} // FeaturePMU

// v8.4a RAS registers
// Op0 Op1 CRn CRm Op2
def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>;
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19 changes: 0 additions & 19 deletions llvm/test/MC/AArch64/armv8.4a-pmu.s
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This file was deleted.

4 changes: 4 additions & 0 deletions llvm/test/MC/AArch64/basic-a64-instructions.s
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Expand Up @@ -3842,6 +3842,7 @@ _func:
msr PMINTENSET_EL1, x12
msr PMINTENCLR_EL1, x12
msr PMOVSSET_EL0, x12
msr PMMIR_EL1, x12
msr MAIR_EL1, x12
msr MAIR_EL2, x12
msr MAIR_EL3, x12
Expand Down Expand Up @@ -4095,6 +4096,7 @@ _func:
// CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12 // encoding: [0x2c,0x9e,0x18,0xd5]
// CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12 // encoding: [0x4c,0x9e,0x18,0xd5]
// CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12 // encoding: [0x6c,0x9e,0x1b,0xd5]
// CHECK: msr {{pmmir_el1|PMMIR_EL1}}, x12 // encoding: [0xcc,0x9e,0x18,0xd5]
// CHECK: msr {{mair_el1|MAIR_EL1}}, x12 // encoding: [0x0c,0xa2,0x18,0xd5]
// CHECK: msr {{mair_el2|MAIR_EL2}}, x12 // encoding: [0x0c,0xa2,0x1c,0xd5]
// CHECK: msr {{mair_el3|MAIR_EL3}}, x12 // encoding: [0x0c,0xa2,0x1e,0xd5]
Expand Down Expand Up @@ -4392,6 +4394,7 @@ _func:
mrs x9, PMINTENSET_EL1
mrs x9, PMINTENCLR_EL1
mrs x9, PMOVSSET_EL0
mrs x9, PMMIR_EL1
mrs x9, MAIR_EL1
mrs x9, MAIR_EL2
mrs x9, MAIR_EL3
Expand Down Expand Up @@ -4694,6 +4697,7 @@ _func:
// CHECK: mrs x9, {{pmintenset_el1|PMINTENSET_EL1}} // encoding: [0x29,0x9e,0x38,0xd5]
// CHECK: mrs x9, {{pmintenclr_el1|PMINTENCLR_EL1}} // encoding: [0x49,0x9e,0x38,0xd5]
// CHECK: mrs x9, {{pmovsset_el0|PMOVSSET_EL0}} // encoding: [0x69,0x9e,0x3b,0xd5]
// CHECK: mrs x9, {{pmmir_el1|PMMIR_EL1}} // encoding: [0xc9,0x9e,0x38,0xd5]
// CHECK: mrs x9, {{mair_el1|MAIR_EL1}} // encoding: [0x09,0xa2,0x38,0xd5]
// CHECK: mrs x9, {{mair_el2|MAIR_EL2}} // encoding: [0x09,0xa2,0x3c,0xd5]
// CHECK: mrs x9, {{mair_el3|MAIR_EL3}} // encoding: [0x09,0xa2,0x3e,0xd5]
Expand Down
10 changes: 0 additions & 10 deletions llvm/test/MC/Disassembler/AArch64/armv8.4a-pmu.txt
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This file was deleted.

4 changes: 4 additions & 0 deletions llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
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Expand Up @@ -3316,6 +3316,7 @@
# CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12
# CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12
# CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12
# CHECK: msr {{pmmir_el1|PMMIR_EL1}}, x12
# CHECK: msr {{mair_el1|MAIR_EL1}}, x12
# CHECK: msr {{mair_el2|MAIR_EL2}}, x12
# CHECK: msr {{mair_el3|MAIR_EL3}}, x12
Expand Down Expand Up @@ -3613,6 +3614,7 @@
# CHECK: mrs x9, {{pmintenset_el1|PMINTENSET_EL1}}
# CHECK: mrs x9, {{pmintenclr_el1|PMINTENCLR_EL1}}
# CHECK: mrs x9, {{pmovsset_el0|PMOVSSET_EL0}}
# CHECK: mrs x9, {{pmmir_el1|PMMIR_EL1}}
# CHECK: mrs x9, {{mair_el1|MAIR_EL1}}
# CHECK: mrs x9, {{mair_el2|MAIR_EL2}}
# CHECK: mrs x9, {{mair_el3|MAIR_EL3}}
Expand Down Expand Up @@ -3874,6 +3876,7 @@
0x2c 0x9e 0x18 0xd5
0x4c 0x9e 0x18 0xd5
0x6c 0x9e 0x1b 0xd5
0xcc 0x9e 0x18 0xd5
0xc 0xa2 0x18 0xd5
0xc 0xa2 0x1c 0xd5
0xc 0xa2 0x1e 0xd5
Expand Down Expand Up @@ -4171,6 +4174,7 @@
0x29 0x9e 0x38 0xd5
0x49 0x9e 0x38 0xd5
0x69 0x9e 0x3b 0xd5
0xc9 0x9e 0x38 0xd5
0x9 0xa2 0x38 0xd5
0x9 0xa2 0x3c 0xd5
0x9 0xa2 0x3e 0xd5
Expand Down

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