[InstCombine][NFC] Precommit tests for https://reviews.llvm.org/D149918

llvm · Oct 20, 2023 · 7ba99fd · 7ba99fd
1 parent a67ae8c
commit 7ba99fd
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diff --git a/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll b/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll
@@ -897,6 +897,19 @@ define i1 @ashrsgt_01_00(i4 %x) {
   ret i1 %c
 }
 
+define i1 @ashrsgt_01_00_multiuse(i4 %x, ptr %p) {
+; CHECK-LABEL: @ashrsgt_01_00_multiuse(
+; CHECK-NEXT:    [[S:%.*]] = ashr i4 [[X:%.*]], 1
+; CHECK-NEXT:    [[C:%.*]] = icmp sgt i4 [[X]], 1
+; CHECK-NEXT:    store i4 [[S]], ptr [[P:%.*]], align 1
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %s = ashr i4 %x, 1
+  %c = icmp sgt i4 %s, 0
+  store i4 %s, ptr %p
+  ret i1 %c
+}
+
 define i1 @ashrsgt_01_01(i4 %x) {
 ; CHECK-LABEL: @ashrsgt_01_01(
 ; CHECK-NEXT:    [[C:%.*]] = icmp sgt i4 [[X:%.*]], 3

diff --git a/llvm/test/Transforms/InstCombine/icmp-shr.ll b/llvm/test/Transforms/InstCombine/icmp-shr.ll
@@ -576,6 +576,19 @@ define i1 @ashr_ugt_0(i4 %x) {
   ret i1 %r
 }
 
+define i1 @ashr_ugt_0_multiuse(i4 %x, ptr %p) {
+; CHECK-LABEL: @ashr_ugt_0_multiuse(
+; CHECK-NEXT:    [[S:%.*]] = ashr i4 [[X:%.*]], 1
+; CHECK-NEXT:    [[R:%.*]] = icmp ugt i4 [[X]], 1
+; CHECK-NEXT:    store i4 [[S]], ptr [[P:%.*]], align 1
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %s = ashr i4 %x, 1
+  %r = icmp ugt i4 %s, 0 ; 0b0000
+  store i4 %s, ptr %p
+  ret i1 %r
+}
+
 define i1 @ashr_ugt_1(i4 %x) {
 ; CHECK-LABEL: @ashr_ugt_1(
 ; CHECK-NEXT:    [[R:%.*]] = icmp ugt i4 [[X:%.*]], 3
@@ -764,6 +777,19 @@ define i1 @ashr_ult_2(i4 %x) {
   ret i1 %r
 }
 
+define i1 @ashr_ult_2_multiuse(i4 %x, ptr %p) {
+; CHECK-LABEL: @ashr_ult_2_multiuse(
+; CHECK-NEXT:    [[S:%.*]] = ashr i4 [[X:%.*]], 1
+; CHECK-NEXT:    [[R:%.*]] = icmp ult i4 [[X]], 4
+; CHECK-NEXT:    store i4 [[S]], ptr [[P:%.*]], align 1
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %s = ashr i4 %x, 1
+  %r = icmp ult i4 %s, 2 ; 0b0010
+  store i4 %s, ptr %p
+  ret i1 %r
+}
+
 ; negative test
 
 define i1 @ashr_ult_3(i4 %x) {

diff --git a/llvm/test/Transforms/PhaseOrdering/icmp-ashr-breaking-select-idiom.ll b/llvm/test/Transforms/PhaseOrdering/icmp-ashr-breaking-select-idiom.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
+; RUN: opt -O1 -S < %s  | FileCheck %s
+
+define i32 @testa(i32 %mul) {
+; CHECK-LABEL: define i32 @testa(
+; CHECK-SAME: i32 [[MUL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[MUL]], 15
+; CHECK-NEXT:    [[CMP4_I:%.*]] = icmp slt i32 [[MUL]], 1073741824
+; CHECK-NEXT:    [[SPEC_SELECT_I:%.*]] = select i1 [[CMP4_I]], i32 [[SHR]], i32 32767
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT_I]]
+;
+  %shr = ashr i32 %mul, 15
+  %cmp4.i = icmp sgt i32 %shr, 32767
+  %switch.i = icmp ult i1 %cmp4.i, true
+  %spec.select.i = select i1 %switch.i, i32 %shr, i32 32767
+  ret i32 %spec.select.i
+}
+
+define i32 @testb(i32 %mul) {
+; CHECK-LABEL: define i32 @testb(
+; CHECK-SAME: i32 [[MUL:%.*]]) local_unnamed_addr #[[ATTR0]] {
+; CHECK-NEXT:    [[SHR102:%.*]] = ashr i32 [[MUL]], 7
+; CHECK-NEXT:    [[CMP4_I:%.*]] = icmp sgt i32 [[MUL]], 16383
+; CHECK-NEXT:    [[RETVAL_0_I:%.*]] = select i1 [[CMP4_I]], i32 127, i32 -128
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[MUL]], 16384
+; CHECK-NEXT:    [[CLEANUP_DEST_SLOT_0_I:%.*]] = icmp ult i32 [[TMP1]], 32768
+; CHECK-NEXT:    [[SPEC_SELECT_I:%.*]] = select i1 [[CLEANUP_DEST_SLOT_0_I]], i32 [[SHR102]], i32 [[RETVAL_0_I]]
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT_I]]
+;
+  %shr102 = ashr i32 %mul, 7
+  %cmp4.i = icmp sgt i32 %shr102, 127
+  %cmp6.i = icmp slt i32 %shr102, -128
+  %retval.0.i = select i1 %cmp4.i, i32 127, i32 -128
+  %cleanup.dest.slot.0.i = select i1 %cmp4.i, i1 true, i1 %cmp6.i
+  %switch.i = icmp ult i1 %cleanup.dest.slot.0.i, true
+  %spec.select.i = select i1 %switch.i, i32 %shr102, i32 %retval.0.i
+  ret i32 %spec.select.i
+}