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AMDGPU/GlobalISel: Add support for G_INTTOPTR
Summary: This is a no-op. Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D52916 llvm-svn: 343839
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34 changes: 34 additions & 0 deletions
34
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir
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# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN | ||
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--- | | ||
define amdgpu_kernel void @inttoptr(i32 addrspace(4)* %const0, i32 addrspace(0)* %flat0) {ret void} | ||
... | ||
--- | ||
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name: inttoptr | ||
legalized: true | ||
regBankSelected: true | ||
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# GCN-LABEL: name: inttoptr | ||
# GCN: [[S64:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1 | ||
# GCN: [[V64:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 | ||
# FIXME: This extra copy is unnecessary, but is it the instruction selector's | ||
# job to clean this up? | ||
# GCN: [[S64_COPY:%[0-9]+]]:sreg_64 = COPY [[S64]] | ||
# GCN: [[VAL:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[S64_COPY]], 0, 0 | ||
# GCN: [[V_VAL:%[0-9]+]]:vgpr_32 = COPY [[VAL]] | ||
# GCN: FLAT_STORE_DWORD [[V64]], [[V_VAL]] | ||
# | ||
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body: | | ||
bb.0: | ||
liveins: $sgpr0_sgpr1, $vgpr0_vgpr1 | ||
%0:sgpr(s64) = COPY $sgpr0_sgpr1 | ||
%1:vgpr(s64) = COPY $vgpr0_vgpr1 | ||
%2:sgpr(p4) = G_INTTOPTR %0 | ||
%3:sgpr(s32) = G_LOAD %2 :: (load 4 from %ir.const0) | ||
%4:vgpr(p0) = G_INTTOPTR %1 | ||
%5:vgpr(s32) = COPY %3 | ||
G_STORE %5, %4 :: (store 4 into %ir.flat0) | ||
... | ||
--- |
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# RUN: llc -march=amdgcn -run-pass=legalizer %s -o - | FileCheck %s | ||
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--- | ||
name: test_inttoptr | ||
body: | | ||
bb.0: | ||
liveins: $sgpr0_sgpr1, $sgpr2, $vgpr0_vgpr1, $vgpr2 | ||
; CHECK-LABEL: name: test_inttoptr | ||
; CHECK: [[S64:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1 | ||
; CHECK: [[S32:%[0-9]+]]:_(s32) = COPY $sgpr2 | ||
; CHECK: [[V64:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 | ||
; CHECK: [[V32:%[0-9]+]]:_(s32) = COPY $vgpr2 | ||
; CHECK: (p0) = G_INTTOPTR [[V64]] | ||
; CHECK: (p1) = G_INTTOPTR [[V64]] | ||
; CHECK: (p3) = G_INTTOPTR [[V32]] | ||
; CHECK: (p4) = G_INTTOPTR [[S64]] | ||
; CHECK: (p5) = G_INTTOPTR [[S32]] | ||
%0:_(s64) = COPY $sgpr0_sgpr1 | ||
%1:_(s32) = COPY $sgpr2 | ||
%2:_(s64) = COPY $vgpr0_vgpr1 | ||
%3:_(s32) = COPY $vgpr2 | ||
%4:_(p0) = G_INTTOPTR %2 | ||
%5:_(p1) = G_INTTOPTR %2 | ||
%6:_(p3) = G_INTTOPTR %3 | ||
%7:_(p4) = G_INTTOPTR %0 | ||
%8:_(p5) = G_INTTOPTR %1 | ||
S_ENDPGM implicit %4, implicit %5, implicit %6, implicit %7, implicit %8 | ||
... |
31 changes: 31 additions & 0 deletions
31
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py | ||
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s | ||
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s | ||
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--- | ||
name: inttoptr_s | ||
legalized: true | ||
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body: | | ||
bb.0: | ||
liveins: $sgpr0_sgpr1 | ||
; CHECK-LABEL: name: inttoptr_s | ||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 | ||
; CHECK: [[INTTOPTR:%[0-9]+]]:sgpr(p4) = G_INTTOPTR [[COPY]](s64) | ||
%0:_(s64) = COPY $sgpr0_sgpr1 | ||
%1:_(p4) = G_INTTOPTR %0 | ||
... | ||
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--- | ||
name: inttoptr_v | ||
legalized: true | ||
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body: | | ||
bb.0: | ||
liveins: $vgpr0_vgpr1 | ||
; CHECK-LABEL: name: inttoptr_v | ||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 | ||
; CHECK: [[INTTOPTR:%[0-9]+]]:vgpr(p0) = G_INTTOPTR [[COPY]](s64) | ||
%0:_(s64) = COPY $vgpr0_vgpr1 | ||
%1:_(p0) = G_INTTOPTR %0 | ||
... |