[RISCV] Add trunc instruction to the __builtin_riscv_ctz_64/__builtin…

…_riscv_clz_64 IR. These builtins were recently changed to return 'int' like the similar __builtin_clz/__builtin_ctz builtins, but the IR generation was not updated to use a truncate.
llvm · Jul 6, 2023 · 7c9230c · 7c9230c
1 parent 1e60ab0
commit 7c9230c
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Showing 3 changed files with 18 additions and 18 deletions.
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -20177,12 +20177,20 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
     case RISCV::BI__builtin_riscv_clz_32:
     case RISCV::BI__builtin_riscv_clz_64: {
       Function *F = CGM.getIntrinsic(Intrinsic::ctlz, Ops[0]->getType());
-      return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+      Value *Result = Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+      if (Result->getType() != ResultType)
+        Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
+                                       "cast");
+      return Result;
     }
     case RISCV::BI__builtin_riscv_ctz_32:
     case RISCV::BI__builtin_riscv_ctz_64: {
       Function *F = CGM.getIntrinsic(Intrinsic::cttz, Ops[0]->getType());
-      return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+      Value *Result = Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+      if (Result->getType() != ResultType)
+        Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
+                                       "cast");
+      return Result;
     }
 
     // Zbc

diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
@@ -29,30 +29,26 @@ int clo_32(int a) {
 
 // RV64XTHEADBB-LABEL: @clz_64(
 // RV64XTHEADBB-NEXT:  entry:
-// RV64XTHEADBB-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 // RV64XTHEADBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 // RV64XTHEADBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
 // RV64XTHEADBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
 // RV64XTHEADBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
-// RV64XTHEADBB-NEXT:    store i64 [[TMP1]], ptr [[RETVAL]], align 4
-// RV64XTHEADBB-NEXT:    [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
-// RV64XTHEADBB-NEXT:    ret i32 [[TMP2]]
+// RV64XTHEADBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64XTHEADBB-NEXT:    ret i32 [[CAST]]
 //
 int clz_64(long a) {
   return __builtin_riscv_clz_64(a);
 }
 
 // RV64XTHEADBB-LABEL: @clo_64(
 // RV64XTHEADBB-NEXT:  entry:
-// RV64XTHEADBB-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 // RV64XTHEADBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 // RV64XTHEADBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
 // RV64XTHEADBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
 // RV64XTHEADBB-NEXT:    [[NOT:%.*]] = xor i64 [[TMP0]], -1
 // RV64XTHEADBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[NOT]], i1 false)
-// RV64XTHEADBB-NEXT:    store i64 [[TMP1]], ptr [[RETVAL]], align 4
-// RV64XTHEADBB-NEXT:    [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
-// RV64XTHEADBB-NEXT:    ret i32 [[TMP2]]
+// RV64XTHEADBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64XTHEADBB-NEXT:    ret i32 [[CAST]]
 //
 int clo_64(long a) {
   return __builtin_riscv_clz_64(~a);

diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -40,14 +40,12 @@ int clz_32(unsigned int a) {
 
 // RV64ZBB-LABEL: @clz_64(
 // RV64ZBB-NEXT:  entry:
-// RV64ZBB-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 // RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 // RV64ZBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
-// RV64ZBB-NEXT:    store i64 [[TMP1]], ptr [[RETVAL]], align 4
-// RV64ZBB-NEXT:    [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
-// RV64ZBB-NEXT:    ret i32 [[TMP2]]
+// RV64ZBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT:    ret i32 [[CAST]]
 //
 int clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
@@ -67,14 +65,12 @@ int ctz_32(unsigned int a) {
 
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
-// RV64ZBB-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 // RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 // RV64ZBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
-// RV64ZBB-NEXT:    store i64 [[TMP1]], ptr [[RETVAL]], align 4
-// RV64ZBB-NEXT:    [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
-// RV64ZBB-NEXT:    ret i32 [[TMP2]]
+// RV64ZBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT:    ret i32 [[CAST]]
 //
 int ctz_64(unsigned long a) {
   return __builtin_riscv_ctz_64(a);