[ARM] f16 constant pool fix

This is a follow up of r325012, that allowed half types in constant pools. Proper alignment was enforced when a big basic block was split up, but not when a CPE was placed before/after a block; the successor block had the wrong alignment. Differential Revision: https://reviews.llvm.org/D43580 llvm-svn: 325754
llvm · Feb 22, 2018 · 7d5909e · 7d5909e
1 parent 971514d
commit 7d5909e
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Showing 4 changed files with 10 additions and 7 deletions.
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -1425,10 +1425,6 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
         assert(!isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL));
 
   NewMBB = splitBlockBeforeInstr(&*MI);
-
-  // 4 byte align the next block after the constant pool when the CPE is a
-  // 16-bit value in ARM mode, and 2 byte for Thumb.
-  NewMBB->setAlignment(isThumb ? 1 : 2);
 }
 
 /// handleConstantPoolUser - Analyze the specified user, checking to see if it
@@ -1489,6 +1485,8 @@ bool ARMConstantIslands::handleConstantPoolUser(unsigned CPUserIndex,
     // We are adding new water.  Update NewWaterList.
     NewWaterList.insert(NewIsland);
   }
+  // Always align the new block because CP entries can be smaller than 4 bytes.
+  NewMBB->setAlignment(isThumb ? 1 : 2);
 
   // Remove the original WaterList entry; we want subsequent insertions in
   // this vicinity to go after the one we're about to insert.  This

diff --git a/llvm/test/CodeGen/ARM/constant-islands-cfg.mir b/llvm/test/CodeGen/ARM/constant-islands-cfg.mir
@@ -39,7 +39,7 @@ fixedStack:
 # CHECK:     successors: %[[LONG_BR_BB:bb.[0-9]+]](0x{{[0-9a-f]+}}), %[[DEST1:bb.[0-9]+]](0x{{[0-9a-f]+}}){{$}}
 # CHECK:     tBcc %[[LONG_BR_BB]], 0, $cpsr
 # CHECK:     tB %[[DEST1]]
-# CHECK: [[LONG_BR_BB]]:
+# CHECK: [[LONG_BR_BB]] (align 1):
 # CHECK:     successors: %[[DEST2:bb.[0-9]+]](0x{{[0-9a-f]+}}){{$}}
 # CHECK:     tB %[[DEST2]]
 # CHECK: [[DEST1]]:
@@ -52,7 +52,7 @@ body:             |
     tBcc %bb.2, 1, killed $cpsr
     tB %bb.3, 14, $noreg
 
-  bb.1:
+  bb.1 (align 1):
     dead $r0 = SPACE 256, undef $r0
 
   bb.2:

diff --git a/llvm/test/CodeGen/ARM/fp16-litpool-arm.mir b/llvm/test/CodeGen/ARM/fp16-litpool-arm.mir
@@ -1,5 +1,7 @@
 # RUN: llc -mtriple=arm-none-eabi -run-pass=arm-cp-islands %s -o - | FileCheck %s
-
+#
+# This checks alignment of a new block when a big basic block is split up.
+#
 --- |
   ; ModuleID = '<stdin>'
   source_filename = "<stdin>"

diff --git a/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir b/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir
@@ -1,4 +1,7 @@
 # RUN: llc -mtriple=thumbv7-none-eabi -run-pass=arm-cp-islands %s -o - | FileCheck %s
+#
+# This checks alignment of a new block when a big basic block is split up.
+#
 --- |
   ; ModuleID = '<stdin>'
   source_filename = "<stdin>"