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Adding skeleton for unit testing Hexagon Code Emission
Adding and modifying CMakeLists.txt files to run unit tests under unittests/Target/* if the directory exists. Adding basic unit test to check that code emitter object can be retrieved. Differential Revision: http://reviews.llvm.org/D5523 Change by: Colin LeMahieu llvm-svn: 218986
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Oct 3, 2014
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add_llvm_library(LLVMHexagonDesc | ||
HexagonMCAsmInfo.cpp | ||
HexagonMCCodeEmitter.cpp | ||
HexagonMCInst.cpp | ||
HexagonMCTargetDesc.cpp | ||
) | ||
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add_dependencies(LLVMHexagonDesc HexagonCommonTableGen) |
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llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
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//===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===// | ||
// | ||
// The LLVM Compiler Infrastructure | ||
// | ||
// This file is distributed under the University of Illinois Open Source | ||
// License. See LICENSE.TXT for details. | ||
// | ||
//===----------------------------------------------------------------------===// | ||
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#include "Hexagon.h" | ||
#include "MCTargetDesc/HexagonBaseInfo.h" | ||
#include "MCTargetDesc/HexagonMCCodeEmitter.h" | ||
#include "MCTargetDesc/HexagonMCTargetDesc.h" | ||
#include "MCTargetDesc/HexagonMCInst.h" | ||
#include "llvm/ADT/Statistic.h" | ||
#include "llvm/MC/MCCodeEmitter.h" | ||
#include "llvm/MC/MCContext.h" | ||
#include "llvm/MC/MCExpr.h" | ||
#include "llvm/MC/MCInst.h" | ||
#include "llvm/MC/MCInstrInfo.h" | ||
#include "llvm/MC/MCRegisterInfo.h" | ||
#include "llvm/MC/MCSubtargetInfo.h" | ||
#include "llvm/Support/Debug.h" | ||
#include "llvm/Support/raw_ostream.h" | ||
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#define DEBUG_TYPE "mccodeemitter" | ||
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using namespace llvm; | ||
using namespace Hexagon; | ||
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); | ||
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namespace { | ||
/// \brief 10.6 Instruction Packets | ||
/// \brief Possible values for instruction packet parse field. | ||
enum class ParseField { duplex = 0x0, last0 = 0x1, last1 = 0x2, end = 0x3 }; | ||
/// \brief Returns the packet bits based on instruction position. | ||
uint32_t getPacketBits(HexagonMCInst const &HMI) { | ||
unsigned const ParseFieldOffset = 14; | ||
ParseField Field = HMI.isPacketEnd() ? ParseField::end : ParseField::last0; | ||
return static_cast <uint32_t> (Field) << ParseFieldOffset; | ||
} | ||
void emitLittleEndian(uint64_t Binary, raw_ostream &OS) { | ||
OS << static_cast<uint8_t>((Binary >> 0x00) & 0xff); | ||
OS << static_cast<uint8_t>((Binary >> 0x08) & 0xff); | ||
OS << static_cast<uint8_t>((Binary >> 0x10) & 0xff); | ||
OS << static_cast<uint8_t>((Binary >> 0x18) & 0xff); | ||
} | ||
} | ||
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HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII, | ||
MCSubtargetInfo const &aMST, | ||
MCContext &aMCT) | ||
: MST(aMST), MCT(aMCT) {} | ||
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void HexagonMCCodeEmitter::EncodeInstruction(MCInst const &MI, raw_ostream &OS, | ||
SmallVectorImpl<MCFixup> &Fixups, | ||
MCSubtargetInfo const &STI) const { | ||
HexagonMCInst const &HMB = static_cast<HexagonMCInst const &>(MI); | ||
uint64_t Binary = getBinaryCodeForInstr(HMB, Fixups, STI) | getPacketBits(HMB); | ||
assert(HMB.getDesc().getSize() == 4 && "All instructions should be 32bit"); | ||
emitLittleEndian(Binary, OS); | ||
++MCNumEmitted; | ||
} | ||
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unsigned | ||
HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO, | ||
SmallVectorImpl<MCFixup> &Fixups, | ||
MCSubtargetInfo const &STI) const { | ||
if (MO.isReg()) | ||
return MCT.getRegisterInfo()->getEncodingValue(MO.getReg()); | ||
if (MO.isImm()) | ||
return static_cast<unsigned>(MO.getImm()); | ||
llvm_unreachable("Only Immediates and Registers implemented right now"); | ||
} | ||
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MCSubtargetInfo const &HexagonMCCodeEmitter::getSubtargetInfo() const { | ||
return MST; | ||
} | ||
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MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII, | ||
MCRegisterInfo const &MRI, | ||
MCSubtargetInfo const &MST, | ||
MCContext &MCT) { | ||
return new HexagonMCCodeEmitter(MII, MST, MCT); | ||
} | ||
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#include "HexagonGenMCCodeEmitter.inc" |
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llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h
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//===-- HexagonMCCodeEmitter.h - Hexagon Target Descriptions ----*- C++ -*-===// | ||
// | ||
// The LLVM Compiler Infrastructure | ||
// | ||
// This file is distributed under the University of Illinois Open Source | ||
// License. See LICENSE.TXT for details. | ||
// | ||
//===----------------------------------------------------------------------===// | ||
/// | ||
/// \file | ||
/// \brief Definition for classes that emit Hexagon machine code from MCInsts | ||
/// | ||
//===----------------------------------------------------------------------===// | ||
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#ifndef HEXAGONMCCODEEMITTER_H | ||
#define HEXAGONMCCODEEMITTER_H | ||
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#include "llvm/MC/MCCodeEmitter.h" | ||
#include "llvm/MC/MCExpr.h" | ||
#include "llvm/MC/MCInst.h" | ||
#include "llvm/MC/MCInstrInfo.h" | ||
#include "llvm/MC/MCRegisterInfo.h" | ||
#include "llvm/MC/MCSubtargetInfo.h" | ||
#include "llvm/Support/raw_ostream.h" | ||
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namespace llvm { | ||
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class HexagonMCCodeEmitter : public MCCodeEmitter { | ||
MCSubtargetInfo const &MST; | ||
MCContext &MCT; | ||
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public: | ||
HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCSubtargetInfo const &aMST, | ||
MCContext &aMCT); | ||
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MCSubtargetInfo const &getSubtargetInfo() const; | ||
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void EncodeInstruction(MCInst const &MI, raw_ostream &OS, | ||
SmallVectorImpl<MCFixup> &Fixups, | ||
MCSubtargetInfo const &STI) const override; | ||
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// getBinaryCodeForInstr - TableGen'erated function for getting the | ||
// binary encoding for an instruction. | ||
uint64_t getBinaryCodeForInstr(MCInst const &MI, | ||
SmallVectorImpl<MCFixup> &Fixups, | ||
MCSubtargetInfo const &STI) const; | ||
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/// \brief Return binary encoding of operand. | ||
unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, | ||
SmallVectorImpl<MCFixup> &Fixups, | ||
MCSubtargetInfo const &STI) const; | ||
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private: | ||
HexagonMCCodeEmitter(HexagonMCCodeEmitter const &) = delete; | ||
void operator=(HexagonMCCodeEmitter const &) = delete; | ||
}; // class HexagonMCCodeEmitter | ||
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} // namespace llvm | ||
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#endif /* HEXAGONMCCODEEMITTER_H */ |
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