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[NFC][X86][Codegen] Add test coverage for interleaved i32 load/store …
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@LebedevRI
LebedevRI committed Sep 29, 2021
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151 changes: 151 additions & 0 deletions llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck --check-prefixes=AVX2 %s
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck --check-prefixes=AVX2 %s
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2,+fast-variable-perlane-shuffle | FileCheck --check-prefixes=AVX2 %s

; These patterns are produced by LoopVectorizer for interleaved stores.

define void @load_i32_stride2_vf2(<4 x i32>* %in.vec, <2 x i32>* %out.vec0, <2 x i32>* %out.vec1) nounwind {
; AVX2-LABEL: load_i32_stride2_vf2:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovaps (%rdi), %xmm0
; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[0,2,2,3]
; AVX2-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,3,2,3]
; AVX2-NEXT: vmovlps %xmm1, (%rsi)
; AVX2-NEXT: vmovlps %xmm0, (%rdx)
; AVX2-NEXT: retq
%wide.vec = load <4 x i32>, <4 x i32>* %in.vec, align 32

%strided.vec0 = shufflevector <4 x i32> %wide.vec, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
%strided.vec1 = shufflevector <4 x i32> %wide.vec, <4 x i32> poison, <2 x i32> <i32 1, i32 3>

store <2 x i32> %strided.vec0, <2 x i32>* %out.vec0, align 32
store <2 x i32> %strided.vec1, <2 x i32>* %out.vec1, align 32

ret void
}

define void @load_i32_stride2_vf4(<8 x i32>* %in.vec, <4 x i32>* %out.vec0, <4 x i32>* %out.vec1) nounwind {
; AVX2-LABEL: load_i32_stride2_vf4:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovaps (%rdi), %xmm0
; AVX2-NEXT: vmovaps 16(%rdi), %xmm1
; AVX2-NEXT: vshufps {{.*#+}} xmm2 = xmm0[0,2],xmm1[0,2]
; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
; AVX2-NEXT: vmovaps %xmm2, (%rsi)
; AVX2-NEXT: vmovaps %xmm0, (%rdx)
; AVX2-NEXT: retq
%wide.vec = load <8 x i32>, <8 x i32>* %in.vec, align 32

%strided.vec0 = shufflevector <8 x i32> %wide.vec, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%strided.vec1 = shufflevector <8 x i32> %wide.vec, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>

store <4 x i32> %strided.vec0, <4 x i32>* %out.vec0, align 32
store <4 x i32> %strided.vec1, <4 x i32>* %out.vec1, align 32

ret void
}

define void @load_i32_stride2_vf8(<16 x i32>* %in.vec, <8 x i32>* %out.vec0, <8 x i32>* %out.vec1) nounwind {
; AVX2-LABEL: load_i32_stride2_vf8:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovaps (%rdi), %ymm0
; AVX2-NEXT: vmovaps 32(%rdi), %ymm1
; AVX2-NEXT: vshufps {{.*#+}} ymm2 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6]
; AVX2-NEXT: vpermpd {{.*#+}} ymm2 = ymm2[0,2,1,3]
; AVX2-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7]
; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-NEXT: vmovaps %ymm2, (%rsi)
; AVX2-NEXT: vmovaps %ymm0, (%rdx)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
%wide.vec = load <16 x i32>, <16 x i32>* %in.vec, align 32

%strided.vec0 = shufflevector <16 x i32> %wide.vec, <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%strided.vec1 = shufflevector <16 x i32> %wide.vec, <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>

store <8 x i32> %strided.vec0, <8 x i32>* %out.vec0, align 32
store <8 x i32> %strided.vec1, <8 x i32>* %out.vec1, align 32

ret void
}

define void @load_i32_stride2_vf16(<32 x i32>* %in.vec, <16 x i32>* %out.vec0, <16 x i32>* %out.vec1) nounwind {
; AVX2-LABEL: load_i32_stride2_vf16:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovaps (%rdi), %ymm0
; AVX2-NEXT: vmovaps 32(%rdi), %ymm1
; AVX2-NEXT: vmovaps 64(%rdi), %ymm2
; AVX2-NEXT: vmovaps 96(%rdi), %ymm3
; AVX2-NEXT: vshufps {{.*#+}} ymm4 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6]
; AVX2-NEXT: vpermpd {{.*#+}} ymm4 = ymm4[0,2,1,3]
; AVX2-NEXT: vshufps {{.*#+}} ymm5 = ymm2[0,2],ymm3[0,2],ymm2[4,6],ymm3[4,6]
; AVX2-NEXT: vpermpd {{.*#+}} ymm5 = ymm5[0,2,1,3]
; AVX2-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7]
; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-NEXT: vshufps {{.*#+}} ymm1 = ymm2[1,3],ymm3[1,3],ymm2[5,7],ymm3[5,7]
; AVX2-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,2,1,3]
; AVX2-NEXT: vmovaps %ymm5, 32(%rsi)
; AVX2-NEXT: vmovaps %ymm4, (%rsi)
; AVX2-NEXT: vmovaps %ymm1, 32(%rdx)
; AVX2-NEXT: vmovaps %ymm0, (%rdx)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
%wide.vec = load <32 x i32>, <32 x i32>* %in.vec, align 32

%strided.vec0 = shufflevector <32 x i32> %wide.vec, <32 x i32> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%strided.vec1 = shufflevector <32 x i32> %wide.vec, <32 x i32> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>

store <16 x i32> %strided.vec0, <16 x i32>* %out.vec0, align 32
store <16 x i32> %strided.vec1, <16 x i32>* %out.vec1, align 32

ret void
}

define void @load_i32_stride2_vf32(<64 x i32>* %in.vec, <32 x i32>* %out.vec0, <32 x i32>* %out.vec1) nounwind {
; AVX2-LABEL: load_i32_stride2_vf32:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovaps (%rdi), %ymm0
; AVX2-NEXT: vmovaps 32(%rdi), %ymm1
; AVX2-NEXT: vmovaps 64(%rdi), %ymm2
; AVX2-NEXT: vmovaps 96(%rdi), %ymm3
; AVX2-NEXT: vmovaps 224(%rdi), %ymm4
; AVX2-NEXT: vmovaps 192(%rdi), %ymm5
; AVX2-NEXT: vmovaps 160(%rdi), %ymm6
; AVX2-NEXT: vmovaps 128(%rdi), %ymm7
; AVX2-NEXT: vshufps {{.*#+}} ymm8 = ymm7[0,2],ymm6[0,2],ymm7[4,6],ymm6[4,6]
; AVX2-NEXT: vpermpd {{.*#+}} ymm8 = ymm8[0,2,1,3]
; AVX2-NEXT: vshufps {{.*#+}} ymm9 = ymm5[0,2],ymm4[0,2],ymm5[4,6],ymm4[4,6]
; AVX2-NEXT: vpermpd {{.*#+}} ymm9 = ymm9[0,2,1,3]
; AVX2-NEXT: vshufps {{.*#+}} ymm10 = ymm2[0,2],ymm3[0,2],ymm2[4,6],ymm3[4,6]
; AVX2-NEXT: vpermpd {{.*#+}} ymm10 = ymm10[0,2,1,3]
; AVX2-NEXT: vshufps {{.*#+}} ymm11 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6]
; AVX2-NEXT: vpermpd {{.*#+}} ymm11 = ymm11[0,2,1,3]
; AVX2-NEXT: vshufps {{.*#+}} ymm4 = ymm5[1,3],ymm4[1,3],ymm5[5,7],ymm4[5,7]
; AVX2-NEXT: vpermpd {{.*#+}} ymm4 = ymm4[0,2,1,3]
; AVX2-NEXT: vshufps {{.*#+}} ymm5 = ymm7[1,3],ymm6[1,3],ymm7[5,7],ymm6[5,7]
; AVX2-NEXT: vpermpd {{.*#+}} ymm5 = ymm5[0,2,1,3]
; AVX2-NEXT: vshufps {{.*#+}} ymm2 = ymm2[1,3],ymm3[1,3],ymm2[5,7],ymm3[5,7]
; AVX2-NEXT: vpermpd {{.*#+}} ymm2 = ymm2[0,2,1,3]
; AVX2-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7]
; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-NEXT: vmovaps %ymm9, 96(%rsi)
; AVX2-NEXT: vmovaps %ymm11, (%rsi)
; AVX2-NEXT: vmovaps %ymm10, 32(%rsi)
; AVX2-NEXT: vmovaps %ymm8, 64(%rsi)
; AVX2-NEXT: vmovaps %ymm5, 64(%rdx)
; AVX2-NEXT: vmovaps %ymm4, 96(%rdx)
; AVX2-NEXT: vmovaps %ymm0, (%rdx)
; AVX2-NEXT: vmovaps %ymm2, 32(%rdx)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
%wide.vec = load <64 x i32>, <64 x i32>* %in.vec, align 32

%strided.vec0 = shufflevector <64 x i32> %wide.vec, <64 x i32> poison, <32 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 32, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 62>
%strided.vec1 = shufflevector <64 x i32> %wide.vec, <64 x i32> poison, <32 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31, i32 33, i32 35, i32 37, i32 39, i32 41, i32 43, i32 45, i32 47, i32 49, i32 51, i32 53, i32 55, i32 57, i32 59, i32 61, i32 63>

store <32 x i32> %strided.vec0, <32 x i32>* %out.vec0, align 32
store <32 x i32> %strided.vec1, <32 x i32>* %out.vec1, align 32

ret void
}
177 changes: 177 additions & 0 deletions llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll
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@@ -0,0 +1,177 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck --check-prefixes=AVX2 %s
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck --check-prefixes=AVX2 %s
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2,+fast-variable-perlane-shuffle | FileCheck --check-prefixes=AVX2 %s

; These patterns are produced by LoopVectorizer for interleaved stores.

define void @store_i32_stride2_vf2(<2 x i32>* %in.vecptr0, <2 x i32>* %in.vecptr1, <4 x i32>* %out.vec) nounwind {
; AVX2-LABEL: store_i32_stride2_vf2:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX2-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX2-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX2-NEXT: vmovaps %xmm0, (%rdx)
; AVX2-NEXT: retq
%in.vec0 = load <2 x i32>, <2 x i32>* %in.vecptr0, align 32
%in.vec1 = load <2 x i32>, <2 x i32>* %in.vecptr1, align 32

%concat01 = shufflevector <2 x i32> %in.vec0, <2 x i32> %in.vec1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%interleaved.vec = shufflevector <4 x i32> %concat01, <4 x i32> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>

store <4 x i32> %interleaved.vec, <4 x i32>* %out.vec, align 32

ret void
}

define void @store_i32_stride2_vf4(<4 x i32>* %in.vecptr0, <4 x i32>* %in.vecptr1, <8 x i32>* %out.vec) nounwind {
; AVX2-LABEL: store_i32_stride2_vf4:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovaps (%rdi), %xmm0
; AVX2-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vmovaps %ymm0, (%rdx)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
%in.vec0 = load <4 x i32>, <4 x i32>* %in.vecptr0, align 32
%in.vec1 = load <4 x i32>, <4 x i32>* %in.vecptr1, align 32

%concat01 = shufflevector <4 x i32> %in.vec0, <4 x i32> %in.vec1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%interleaved.vec = shufflevector <8 x i32> %concat01, <8 x i32> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>

store <8 x i32> %interleaved.vec, <8 x i32>* %out.vec, align 32

ret void
}

define void @store_i32_stride2_vf8(<8 x i32>* %in.vecptr0, <8 x i32>* %in.vecptr1, <16 x i32>* %out.vec) nounwind {
; AVX2-LABEL: store_i32_stride2_vf8:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovaps (%rsi), %xmm0
; AVX2-NEXT: vmovaps 16(%rsi), %xmm1
; AVX2-NEXT: vmovaps (%rdi), %xmm2
; AVX2-NEXT: vmovaps 16(%rdi), %xmm3
; AVX2-NEXT: vunpckhps {{.*#+}} xmm4 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; AVX2-NEXT: vunpckhps {{.*#+}} xmm2 = xmm3[2],xmm1[2],xmm3[3],xmm1[3]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; AVX2-NEXT: vmovaps %xmm1, 32(%rdx)
; AVX2-NEXT: vmovaps %xmm2, 48(%rdx)
; AVX2-NEXT: vmovaps %xmm0, (%rdx)
; AVX2-NEXT: vmovaps %xmm4, 16(%rdx)
; AVX2-NEXT: retq
%in.vec0 = load <8 x i32>, <8 x i32>* %in.vecptr0, align 32
%in.vec1 = load <8 x i32>, <8 x i32>* %in.vecptr1, align 32

%concat01 = shufflevector <8 x i32> %in.vec0, <8 x i32> %in.vec1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%interleaved.vec = shufflevector <16 x i32> %concat01, <16 x i32> poison, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>

store <16 x i32> %interleaved.vec, <16 x i32>* %out.vec, align 32

ret void
}

define void @store_i32_stride2_vf16(<16 x i32>* %in.vecptr0, <16 x i32>* %in.vecptr1, <32 x i32>* %out.vec) nounwind {
; AVX2-LABEL: store_i32_stride2_vf16:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovaps (%rsi), %xmm0
; AVX2-NEXT: vmovaps 16(%rsi), %xmm1
; AVX2-NEXT: vmovaps 32(%rsi), %xmm2
; AVX2-NEXT: vmovaps 48(%rsi), %xmm3
; AVX2-NEXT: vmovaps (%rdi), %xmm4
; AVX2-NEXT: vmovaps 16(%rdi), %xmm5
; AVX2-NEXT: vmovaps 32(%rdi), %xmm6
; AVX2-NEXT: vmovaps 48(%rdi), %xmm7
; AVX2-NEXT: vunpckhps {{.*#+}} xmm8 = xmm6[2],xmm2[2],xmm6[3],xmm2[3]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm2 = xmm6[0],xmm2[0],xmm6[1],xmm2[1]
; AVX2-NEXT: vunpckhps {{.*#+}} xmm6 = xmm7[2],xmm3[2],xmm7[3],xmm3[3]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm3 = xmm7[0],xmm3[0],xmm7[1],xmm3[1]
; AVX2-NEXT: vunpckhps {{.*#+}} xmm7 = xmm5[2],xmm1[2],xmm5[3],xmm1[3]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm1 = xmm5[0],xmm1[0],xmm5[1],xmm1[1]
; AVX2-NEXT: vunpckhps {{.*#+}} xmm5 = xmm4[2],xmm0[2],xmm4[3],xmm0[3]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm0 = xmm4[0],xmm0[0],xmm4[1],xmm0[1]
; AVX2-NEXT: vmovaps %xmm0, (%rdx)
; AVX2-NEXT: vmovaps %xmm5, 16(%rdx)
; AVX2-NEXT: vmovaps %xmm1, 32(%rdx)
; AVX2-NEXT: vmovaps %xmm7, 48(%rdx)
; AVX2-NEXT: vmovaps %xmm3, 96(%rdx)
; AVX2-NEXT: vmovaps %xmm6, 112(%rdx)
; AVX2-NEXT: vmovaps %xmm2, 64(%rdx)
; AVX2-NEXT: vmovaps %xmm8, 80(%rdx)
; AVX2-NEXT: retq
%in.vec0 = load <16 x i32>, <16 x i32>* %in.vecptr0, align 32
%in.vec1 = load <16 x i32>, <16 x i32>* %in.vecptr1, align 32

%concat01 = shufflevector <16 x i32> %in.vec0, <16 x i32> %in.vec1, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
%interleaved.vec = shufflevector <32 x i32> %concat01, <32 x i32> poison, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>

store <32 x i32> %interleaved.vec, <32 x i32>* %out.vec, align 32

ret void
}

define void @store_i32_stride2_vf32(<32 x i32>* %in.vecptr0, <32 x i32>* %in.vecptr1, <64 x i32>* %out.vec) nounwind {
; AVX2-LABEL: store_i32_stride2_vf32:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovaps 64(%rsi), %xmm1
; AVX2-NEXT: vmovaps 64(%rdi), %xmm2
; AVX2-NEXT: vunpckhps {{.*#+}} xmm0 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; AVX2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-NEXT: vunpcklps {{.*#+}} xmm9 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX2-NEXT: vmovaps 80(%rsi), %xmm3
; AVX2-NEXT: vmovaps 80(%rdi), %xmm4
; AVX2-NEXT: vunpckhps {{.*#+}} xmm10 = xmm4[2],xmm3[2],xmm4[3],xmm3[3]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm11 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; AVX2-NEXT: vmovaps (%rsi), %xmm4
; AVX2-NEXT: vmovaps 16(%rsi), %xmm5
; AVX2-NEXT: vmovaps 32(%rsi), %xmm6
; AVX2-NEXT: vmovaps 48(%rsi), %xmm7
; AVX2-NEXT: vmovaps (%rdi), %xmm0
; AVX2-NEXT: vmovaps 16(%rdi), %xmm1
; AVX2-NEXT: vmovaps 32(%rdi), %xmm2
; AVX2-NEXT: vmovaps 48(%rdi), %xmm3
; AVX2-NEXT: vunpckhps {{.*#+}} xmm12 = xmm1[2],xmm5[2],xmm1[3],xmm5[3]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm13 = xmm1[0],xmm5[0],xmm1[1],xmm5[1]
; AVX2-NEXT: vunpckhps {{.*#+}} xmm14 = xmm0[2],xmm4[2],xmm0[3],xmm4[3]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm15 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
; AVX2-NEXT: vunpckhps {{.*#+}} xmm8 = xmm3[2],xmm7[2],xmm3[3],xmm7[3]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm4 = xmm3[0],xmm7[0],xmm3[1],xmm7[1]
; AVX2-NEXT: vunpckhps {{.*#+}} xmm7 = xmm2[2],xmm6[2],xmm2[3],xmm6[3]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm3 = xmm2[0],xmm6[0],xmm2[1],xmm6[1]
; AVX2-NEXT: vmovaps 112(%rsi), %xmm6
; AVX2-NEXT: vmovaps 112(%rdi), %xmm1
; AVX2-NEXT: vunpckhps {{.*#+}} xmm5 = xmm1[2],xmm6[2],xmm1[3],xmm6[3]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm2 = xmm1[0],xmm6[0],xmm1[1],xmm6[1]
; AVX2-NEXT: vmovaps 96(%rsi), %xmm6
; AVX2-NEXT: vmovaps 96(%rdi), %xmm0
; AVX2-NEXT: vunpckhps {{.*#+}} xmm1 = xmm0[2],xmm6[2],xmm0[3],xmm6[3]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[1]
; AVX2-NEXT: vmovaps %xmm0, 192(%rdx)
; AVX2-NEXT: vmovaps %xmm1, 208(%rdx)
; AVX2-NEXT: vmovaps %xmm2, 224(%rdx)
; AVX2-NEXT: vmovaps %xmm5, 240(%rdx)
; AVX2-NEXT: vmovaps %xmm3, 64(%rdx)
; AVX2-NEXT: vmovaps %xmm7, 80(%rdx)
; AVX2-NEXT: vmovaps %xmm4, 96(%rdx)
; AVX2-NEXT: vmovaps %xmm8, 112(%rdx)
; AVX2-NEXT: vmovaps %xmm15, (%rdx)
; AVX2-NEXT: vmovaps %xmm14, 16(%rdx)
; AVX2-NEXT: vmovaps %xmm13, 32(%rdx)
; AVX2-NEXT: vmovaps %xmm12, 48(%rdx)
; AVX2-NEXT: vmovaps %xmm11, 160(%rdx)
; AVX2-NEXT: vmovaps %xmm10, 176(%rdx)
; AVX2-NEXT: vmovaps %xmm9, 128(%rdx)
; AVX2-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; AVX2-NEXT: vmovaps %xmm0, 144(%rdx)
; AVX2-NEXT: retq
%in.vec0 = load <32 x i32>, <32 x i32>* %in.vecptr0, align 32
%in.vec1 = load <32 x i32>, <32 x i32>* %in.vecptr1, align 32

%concat01 = shufflevector <32 x i32> %in.vec0, <32 x i32> %in.vec1, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
%interleaved.vec = shufflevector <64 x i32> %concat01, <64 x i32> poison, <64 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63>

store <64 x i32> %interleaved.vec, <64 x i32>* %out.vec, align 32

ret void
}

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