[RISCV][test] Add explicit dso_local to definitions in ELF static rel…

…ocation model tests
llvm · Dec 30, 2020 · 7e5508e · 7e5508e
1 parent a90e5a8
commit 7e5508e
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Showing 7 changed files with 72 additions and 72 deletions.
diff --git a/llvm/test/CodeGen/RISCV/double-mem.ll b/llvm/test/CodeGen/RISCV/double-mem.ll
@@ -4,7 +4,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IFD %s
 
-define double @fld(double *%a) nounwind {
+define dso_local double @fld(double *%a) nounwind {
 ; RV32IFD-LABEL: fld:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
@@ -33,7 +33,7 @@ define double @fld(double *%a) nounwind {
   ret double %4
 }
 
-define void @fsd(double *%a, double %b, double %c) nounwind {
+define dso_local void @fsd(double *%a, double %b, double %c) nounwind {
 ; RV32IFD-LABEL: fsd:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
@@ -67,9 +67,9 @@ define void @fsd(double *%a, double %b, double %c) nounwind {
 }
 
 ; Check load and store to a global
-@G = global double 0.0
+@G = dso_local global double 0.0
 
-define double @fld_fsd_global(double %a, double %b) nounwind {
+define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: fld_fsd_global:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
@@ -117,7 +117,7 @@ define double @fld_fsd_global(double %a, double %b) nounwind {
 }
 
 ; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
-define double @fld_fsd_constant(double %a) nounwind {
+define dso_local double @fld_fsd_constant(double %a) nounwind {
 ; RV32IFD-LABEL: fld_fsd_constant:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
@@ -154,7 +154,7 @@ define double @fld_fsd_constant(double %a) nounwind {
 
 declare void @notdead(i8*)
 
-define double @fld_stack(double %a) nounwind {
+define dso_local double @fld_stack(double %a) nounwind {
 ; RV32IFD-LABEL: fld_stack:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -32
@@ -198,7 +198,7 @@ define double @fld_stack(double %a) nounwind {
   ret double %4
 }
 
-define void @fsd_stack(double %a, double %b) nounwind {
+define dso_local void @fsd_stack(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: fsd_stack:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -32
@@ -239,7 +239,7 @@ define void @fsd_stack(double %a, double %b) nounwind {
 }
 
 ; Test selection of store<ST4[%a], trunc to f32>, ..
-define void @fsd_trunc(float* %a, double %b) nounwind noinline optnone {
+define dso_local void @fsd_trunc(float* %a, double %b) nounwind noinline optnone {
 ; RV32IFD-LABEL: fsd_trunc:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16

diff --git a/llvm/test/CodeGen/RISCV/float-mem.ll b/llvm/test/CodeGen/RISCV/float-mem.ll
@@ -4,7 +4,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IF %s
 
-define float @flw(float *%a) nounwind {
+define dso_local float @flw(float *%a) nounwind {
 ; RV32IF-LABEL: flw:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    flw ft0, 0(a0)
@@ -29,7 +29,7 @@ define float @flw(float *%a) nounwind {
   ret float %4
 }
 
-define void @fsw(float *%a, float %b, float %c) nounwind {
+define dso_local void @fsw(float *%a, float %b, float %c) nounwind {
 ; Use %b and %c in an FP op to ensure floating point registers are used, even
 ; for the soft float ABI
 ; RV32IF-LABEL: fsw:
@@ -57,9 +57,9 @@ define void @fsw(float *%a, float %b, float %c) nounwind {
 }
 
 ; Check load and store to a global
-@G = global float 0.0
+@G = dso_local global float 0.0
 
-define float @flw_fsw_global(float %a, float %b) nounwind {
+define dso_local float @flw_fsw_global(float %a, float %b) nounwind {
 ; Use %a and %b in an FP op to ensure floating point registers are used, even
 ; for the soft float ABI
 ; RV32IF-LABEL: flw_fsw_global:
@@ -99,7 +99,7 @@ define float @flw_fsw_global(float %a, float %b) nounwind {
 }
 
 ; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
-define float @flw_fsw_constant(float %a) nounwind {
+define dso_local float @flw_fsw_constant(float %a) nounwind {
 ; RV32IF-LABEL: flw_fsw_constant:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    lui a1, 912092
@@ -130,7 +130,7 @@ define float @flw_fsw_constant(float %a) nounwind {
 
 declare void @notdead(i8*)
 
-define float @flw_stack(float %a) nounwind {
+define dso_local float @flw_stack(float %a) nounwind {
 ; RV32IF-LABEL: flw_stack:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
@@ -170,7 +170,7 @@ define float @flw_stack(float %a) nounwind {
   ret float %4
 }
 
-define void @fsw_stack(float %a, float %b) nounwind {
+define dso_local void @fsw_stack(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fsw_stack:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16

diff --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
@@ -11,14 +11,14 @@
 ; Check if we do the fold under various conditions. If off1 is (the low part of)
 ; an address the fold's safety depends on the variable's alignment.
 
-@g_0 = global i64 0
-@g_1 = global i64 0, align 1
-@g_2 = global i64 0, align 2
-@g_4 = global i64 0, align 4
-@g_8 = global i64 0, align 8
-@g_16 = global i64 0, align 16
+@g_0 = dso_local global i64 0
+@g_1 = dso_local global i64 0, align 1
+@g_2 = dso_local global i64 0, align 2
+@g_4 = dso_local global i64 0, align 4
+@g_8 = dso_local global i64 0, align 8
+@g_16 = dso_local global i64 0, align 16
 
-define i64 @load_g_0() nounwind {
+define dso_local i64 @load_g_0() nounwind {
 ; RV32I-LABEL: load_g_0:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a1, %hi(g_0)
@@ -36,7 +36,7 @@ entry:
   ret i64 %0
 }
 
-define i64 @load_g_1() nounwind {
+define dso_local i64 @load_g_1() nounwind {
 ; RV32I-LABEL: load_g_1:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a1, %hi(g_1)
@@ -55,7 +55,7 @@ entry:
   ret i64 %0
 }
 
-define i64 @load_g_2() nounwind {
+define dso_local i64 @load_g_2() nounwind {
 ; RV32I-LABEL: load_g_2:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a1, %hi(g_2)
@@ -74,7 +74,7 @@ entry:
   ret i64 %0
 }
 
-define i64 @load_g_4() nounwind {
+define dso_local i64 @load_g_4() nounwind {
 ; RV32I-LABEL: load_g_4:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a1, %hi(g_4)
@@ -93,7 +93,7 @@ entry:
   ret i64 %0
 }
 
-define i64 @load_g_8() nounwind {
+define dso_local i64 @load_g_8() nounwind {
 ; RV32I-LABEL: load_g_8:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a1, %hi(g_8)
@@ -111,7 +111,7 @@ entry:
   ret i64 %0
 }
 
-define i64 @load_g_16() nounwind {
+define dso_local i64 @load_g_16() nounwind {
 ; RV32I-LABEL: load_g_16:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a1, %hi(g_16)
@@ -129,7 +129,7 @@ entry:
   ret i64 %0
 }
 
-define void @store_g_4() nounwind {
+define dso_local void @store_g_4() nounwind {
 ; RV32I-LABEL: store_g_4:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %hi(g_4)
@@ -148,7 +148,7 @@ entry:
    ret void
 }
 
-define void @store_g_8() nounwind {
+define dso_local void @store_g_8() nounwind {
 ; RV32I-LABEL: store_g_8:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %hi(g_8)
@@ -171,7 +171,7 @@ entry:
 @ga_8 = dso_local local_unnamed_addr global [2 x i64] zeroinitializer, align 8
 @ga_16 = dso_local local_unnamed_addr global [2 x i64] zeroinitializer, align 16
 
-define i64 @load_ga_8() nounwind {
+define dso_local i64 @load_ga_8() nounwind {
 ; RV32I-LABEL: load_ga_8:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %hi(ga_8)
@@ -190,7 +190,7 @@ entry:
   ret i64 %0
 }
 
-define i64 @load_ga_16() nounwind {
+define dso_local i64 @load_ga_16() nounwind {
 ; RV32I-LABEL: load_ga_16:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a1, %hi(ga_16)
@@ -210,10 +210,10 @@ entry:
 
 ; Check for folds in accesses to thread-local variables.
 
-@tl_4 = thread_local global i64 0, align 4
-@tl_8 = thread_local global i64 0, align 8
+@tl_4 = dso_local thread_local global i64 0, align 4
+@tl_8 = dso_local thread_local global i64 0, align 8
 
-define i64 @load_tl_4() nounwind {
+define dso_local i64 @load_tl_4() nounwind {
 ; RV32I-LABEL: load_tl_4:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %tprel_hi(tl_4)
@@ -234,7 +234,7 @@ entry:
   ret i64 %0
 }
 
-define i64 @load_tl_8() nounwind {
+define dso_local i64 @load_tl_8() nounwind {
 ; RV32I-LABEL: load_tl_8:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %tprel_hi(tl_8)
@@ -254,7 +254,7 @@ entry:
   ret i64 %0
 }
 
-define i64 @load_const_ok() nounwind {
+define dso_local i64 @load_const_ok() nounwind {
 ; RV32I-LABEL: load_const_ok:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lw a0, 2040(zero)
@@ -270,7 +270,7 @@ entry:
   ret i64 %0
 }
 
-define i64 @load_cost_overflow() nounwind {
+define dso_local i64 @load_cost_overflow() nounwind {
 ; RV32I-LABEL: load_cost_overflow:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, 1

diff --git a/llvm/test/CodeGen/RISCV/half-mem.ll b/llvm/test/CodeGen/RISCV/half-mem.ll
@@ -27,7 +27,7 @@ define half @flh(half *%a) nounwind {
   ret half %4
 }
 
-define void @fsh(half *%a, half %b, half %c) nounwind {
+define dso_local void @fsh(half *%a, half %b, half %c) nounwind {
 ; Use %b and %c in an FP op to ensure half precision floating point registers
 ; are used, even for the soft half ABI
 ; RV32IZFH-LABEL: fsh:
@@ -51,7 +51,7 @@ define void @fsh(half *%a, half %b, half %c) nounwind {
 }
 
 ; Check load and store to a global
-@G = global half 0.0
+@G = dso_local global half 0.0
 
 define half @flh_fsh_global(half %a, half %b) nounwind {
 ; Use %a and %b in an FP op to ensure half precision floating point registers
@@ -152,7 +152,7 @@ define half @flh_stack(half %a) nounwind {
   ret half %4
 }
 
-define void @fsh_stack(half %a, half %b) nounwind {
+define dso_local void @fsh_stack(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fsh_stack:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16