[InstCombine] Infer disjoint flag on Or instructions. (#72912)

The disjoint flag was recently added to IR in #72583

We already set it when we turn an add into an or. This patch sets it on Ors that weren't converted from an Add.

clang/test/Headers/__clang_hip_math.hip

@@ -2451,7 +2451,7 @@ extern "C" __device__ double test_modf(double x, double* y) {
 // CHECK-NEXT:    [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, [[CLEANUP_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_COND_I_I_I]] ], [ 0, [[CLEANUP_I36_I_I]] ], [ [[__R_0_I32_I_I]], [[WHILE_COND_I30_I_I]] ], [ 0, [[CLEANUP_I20_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_COND_I14_I_I]] ]
 // CHECK-NEXT:    [[CONV_I:%.*]] = trunc i64 [[RETVAL_0_I_I]] to i32
 // CHECK-NEXT:    [[BF_VALUE_I:%.*]] = and i32 [[CONV_I]], 4194303
-// CHECK-NEXT:    [[BF_SET9_I:%.*]] = or i32 [[BF_VALUE_I]], 2143289344
+// CHECK-NEXT:    [[BF_SET9_I:%.*]] = or disjoint i32 [[BF_VALUE_I]], 2143289344
 // CHECK-NEXT:    [[TMP10:%.*]] = bitcast i32 [[BF_SET9_I]] to float
 // CHECK-NEXT:    ret float [[TMP10]]
 //
@@ -2549,7 +2549,7 @@ extern "C" __device__ float test_nanf(const char *tag) {
 // CHECK:       _ZL3nanPKc.exit:
 // CHECK-NEXT:    [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, [[CLEANUP_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_COND_I_I_I]] ], [ 0, [[CLEANUP_I36_I_I]] ], [ [[__R_0_I32_I_I]], [[WHILE_COND_I30_I_I]] ], [ 0, [[CLEANUP_I20_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_COND_I14_I_I]] ]
 // CHECK-NEXT:    [[BF_VALUE_I:%.*]] = and i64 [[RETVAL_0_I_I]], 2251799813685247
-// CHECK-NEXT:    [[BF_SET9_I:%.*]] = or i64 [[BF_VALUE_I]], 9221120237041090560
+// CHECK-NEXT:    [[BF_SET9_I:%.*]] = or disjoint i64 [[BF_VALUE_I]], 9221120237041090560
 // CHECK-NEXT:    [[TMP10:%.*]] = bitcast i64 [[BF_SET9_I]] to double
 // CHECK-NEXT:    ret double [[TMP10]]
 //

llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

@@ -264,6 +264,16 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
     if (ShrinkDemandedConstant(I, 1, DemandedMask))
       return I;
 
+    // Infer disjoint flag if no common bits are set.
+    if (!cast<PossiblyDisjointInst>(I)->isDisjoint()) {
+      WithCache<const Value *> LHSCache(I->getOperand(0), LHSKnown),
+          RHSCache(I->getOperand(1), RHSKnown);
+      if (haveNoCommonBitsSet(LHSCache, RHSCache, SQ.getWithInstruction(I))) {
+        cast<PossiblyDisjointInst>(I)->setIsDisjoint(true);
+        return I;
+      }
+    }
+
     break;
   }
   case Instruction::Xor: {

llvm/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll

@@ -33,9 +33,9 @@ define i8 @foo(i8 %arg, i8 %arg1) {
 ; CHECK-NEXT:    [[T4:%.*]] = and i8 [[ARG1]], 33
 ; CHECK-NEXT:    [[T5:%.*]] = sub nsw i8 40, [[T2]]
 ; CHECK-NEXT:    [[T6:%.*]] = and i8 [[T5]], 84
-; CHECK-NEXT:    [[T7:%.*]] = or i8 [[T4]], [[T6]]
+; CHECK-NEXT:    [[T7:%.*]] = or disjoint i8 [[T4]], [[T6]]
 ; CHECK-NEXT:    [[T8:%.*]] = xor i8 [[T]], [[T3]]
-; CHECK-NEXT:    [[T9:%.*]] = or i8 [[T7]], [[T8]]
+; CHECK-NEXT:    [[T9:%.*]] = or disjoint i8 [[T7]], [[T8]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = lshr i8 [[T8]], 2
 ; CHECK-NEXT:    [[T11:%.*]] = and i8 [[TMP1]], 32
 ; CHECK-NEXT:    [[T12:%.*]] = xor i8 [[T11]], [[T9]]

llvm/test/Transforms/InstCombine/add.ll

@@ -764,7 +764,7 @@ define i32 @test29(i32 %x, i32 %y) {
 ; CHECK-NEXT:    [[TMP_2:%.*]] = sub i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[TMP_7:%.*]] = and i32 [[X]], 63
 ; CHECK-NEXT:    [[TMP_9:%.*]] = and i32 [[TMP_2]], -64
-; CHECK-NEXT:    [[TMP_10:%.*]] = or i32 [[TMP_7]], [[TMP_9]]
+; CHECK-NEXT:    [[TMP_10:%.*]] = or disjoint i32 [[TMP_7]], [[TMP_9]]
 ; CHECK-NEXT:    ret i32 [[TMP_10]]
 ;
   %tmp.2 = sub i32 %x, %y
@@ -1499,7 +1499,7 @@ define i8 @add_like_or_n1(i8 %x) {
 define i8 @add_like_or_t2_extrause(i8 %x) {
 ; CHECK-LABEL: @add_like_or_t2_extrause(
 ; CHECK-NEXT:    [[I0:%.*]] = shl i8 [[X:%.*]], 4
-; CHECK-NEXT:    [[I1:%.*]] = or i8 [[I0]], 15
+; CHECK-NEXT:    [[I1:%.*]] = or disjoint i8 [[I0]], 15
 ; CHECK-NEXT:    call void @use(i8 [[I1]])
 ; CHECK-NEXT:    [[R:%.*]] = add i8 [[I0]], 57
 ; CHECK-NEXT:    ret i8 [[R]]
@@ -2361,7 +2361,7 @@ define { i64, i64 } @PR57576(i64 noundef %x, i64 noundef %y, i64 noundef %z, i64
 ; CHECK-NEXT:    [[ZY:%.*]] = zext i64 [[Y:%.*]] to i128
 ; CHECK-NEXT:    [[ZZ:%.*]] = zext i64 [[Z:%.*]] to i128
 ; CHECK-NEXT:    [[SHY:%.*]] = shl nuw i128 [[ZY]], 64
-; CHECK-NEXT:    [[XY:%.*]] = or i128 [[SHY]], [[ZX]]
+; CHECK-NEXT:    [[XY:%.*]] = or disjoint i128 [[SHY]], [[ZX]]
 ; CHECK-NEXT:    [[SUB:%.*]] = sub i128 [[XY]], [[ZZ]]
 ; CHECK-NEXT:    [[T:%.*]] = trunc i128 [[SUB]] to i64
 ; CHECK-NEXT:    [[TMP1:%.*]] = lshr i128 [[SUB]], 64

llvm/test/Transforms/InstCombine/and-or-not.ll

@@ -553,7 +553,7 @@ define i32 @or_to_nxor_multiuse(i32 %a, i32 %b) {
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[A]], [[B]]
 ; CHECK-NEXT:    [[NOTOR:%.*]] = xor i32 [[OR]], -1
-; CHECK-NEXT:    [[OR2:%.*]] = or i32 [[AND]], [[NOTOR]]
+; CHECK-NEXT:    [[OR2:%.*]] = or disjoint i32 [[AND]], [[NOTOR]]
 ; CHECK-NEXT:    [[MUL1:%.*]] = mul i32 [[AND]], [[NOTOR]]
 ; CHECK-NEXT:    [[MUL2:%.*]] = mul i32 [[MUL1]], [[OR2]]
 ; CHECK-NEXT:    ret i32 [[MUL2]]

llvm/test/Transforms/InstCombine/and-or.ll

@@ -217,7 +217,7 @@ define i8 @or_and2_or2(i8 %x) {
 ; CHECK-NEXT:    [[X2:%.*]] = and i8 [[O2]], 66
 ; CHECK-NEXT:    call void @use(i8 [[X2]])
 ; CHECK-NEXT:    [[BITFIELD:%.*]] = and i8 [[X]], -8
-; CHECK-NEXT:    [[R:%.*]] = or i8 [[BITFIELD]], 3
+; CHECK-NEXT:    [[R:%.*]] = or disjoint i8 [[BITFIELD]], 3
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %o1 = or i8 %x, 1
@@ -243,7 +243,7 @@ define <2 x i8> @or_and2_or2_splat(<2 x i8> %x) {
 ; CHECK-NEXT:    [[X2:%.*]] = and <2 x i8> [[O2]], <i8 66, i8 66>
 ; CHECK-NEXT:    call void @use_vec(<2 x i8> [[X2]])
 ; CHECK-NEXT:    [[BITFIELD:%.*]] = and <2 x i8> [[X]], <i8 -8, i8 -8>
-; CHECK-NEXT:    [[R:%.*]] = or <2 x i8> [[BITFIELD]], <i8 3, i8 3>
+; CHECK-NEXT:    [[R:%.*]] = or disjoint <2 x i8> [[BITFIELD]], <i8 3, i8 3>
 ; CHECK-NEXT:    ret <2 x i8> [[R]]
 ;
   %o1 = or <2 x i8> %x, <i8 1, i8 1>
@@ -355,7 +355,7 @@ define i64 @or_or_and_complex(i64 %i) {
 ; CHECK-NEXT:    [[TMP2:%.*]] = shl i64 [[I]], 8
 ; CHECK-NEXT:    [[TMP3:%.*]] = and i64 [[TMP1]], 71777214294589695
 ; CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP2]], -71777214294589696
-; CHECK-NEXT:    [[OR27:%.*]] = or i64 [[TMP3]], [[TMP4]]
+; CHECK-NEXT:    [[OR27:%.*]] = or disjoint i64 [[TMP3]], [[TMP4]]
 ; CHECK-NEXT:    ret i64 [[OR27]]
 ;
   %1 = lshr i64 %i, 8

llvm/test/Transforms/InstCombine/and.ll

@@ -2433,7 +2433,7 @@ define i8 @negate_lowbitmask_use2(i8 %x, i8 %y) {
 define i64 @test_and_or_constexpr_infloop() {
 ; CHECK-LABEL: @test_and_or_constexpr_infloop(
 ; CHECK-NEXT:    [[AND:%.*]] = and i64 ptrtoint (ptr @g to i64), -8
-; CHECK-NEXT:    [[OR:%.*]] = or i64 [[AND]], 1
+; CHECK-NEXT:    [[OR:%.*]] = or disjoint i64 [[AND]], 1
 ; CHECK-NEXT:    ret i64 [[OR]]
 ;
   %and = and i64 ptrtoint (ptr @g to i64), -8

llvm/test/Transforms/InstCombine/apint-shift.ll

@@ -273,7 +273,7 @@ define i18 @test13(i18 %x) {
 define i35 @test14(i35 %A) {
 ; CHECK-LABEL: @test14(
 ; CHECK-NEXT:    [[B:%.*]] = and i35 [[A:%.*]], -19760
-; CHECK-NEXT:    [[C:%.*]] = or i35 [[B]], 19744
+; CHECK-NEXT:    [[C:%.*]] = or disjoint i35 [[B]], 19744
 ; CHECK-NEXT:    ret i35 [[C]]
 ;
   %B = lshr i35 %A, 4

llvm/test/Transforms/InstCombine/binop-and-shifts.ll

@@ -365,7 +365,7 @@ define i8 @lshr_xor_or_good_mask(i8 %x, i8 %y) {
 ; CHECK-LABEL: @lshr_xor_or_good_mask(
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i8 [[TMP1]], 4
-; CHECK-NEXT:    [[BW1:%.*]] = or i8 [[TMP2]], 48
+; CHECK-NEXT:    [[BW1:%.*]] = or disjoint i8 [[TMP2]], 48
 ; CHECK-NEXT:    ret i8 [[BW1]]
 ;
   %shift1 = lshr i8 %x, 4

llvm/test/Transforms/InstCombine/binop-of-displaced-shifts.ll

@@ -271,7 +271,7 @@ define i8 @mismatched_shifts(i8 %x) {
 ; CHECK-NEXT:    [[SHIFT:%.*]] = shl i8 16, [[X]]
 ; CHECK-NEXT:    [[ADD:%.*]] = add i8 [[X]], 1
 ; CHECK-NEXT:    [[SHIFT2:%.*]] = lshr i8 3, [[ADD]]
-; CHECK-NEXT:    [[BINOP:%.*]] = or i8 [[SHIFT]], [[SHIFT2]]
+; CHECK-NEXT:    [[BINOP:%.*]] = or disjoint i8 [[SHIFT]], [[SHIFT2]]
 ; CHECK-NEXT:    ret i8 [[BINOP]]
 ;
   %shift = shl i8 16, %x

llvm/test/Transforms/InstCombine/bitcast-inselt-bitcast.ll

@@ -17,7 +17,7 @@ define i16 @insert0_v2i8(i16 %x, i8 %y) {
 ; LE-LABEL: @insert0_v2i8(
 ; LE-NEXT:    [[TMP1:%.*]] = and i16 [[X:%.*]], -256
 ; LE-NEXT:    [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i16
-; LE-NEXT:    [[R:%.*]] = or i16 [[TMP1]], [[TMP2]]
+; LE-NEXT:    [[R:%.*]] = or disjoint i16 [[TMP1]], [[TMP2]]
 ; LE-NEXT:    ret i16 [[R]]
 ;
   %v = bitcast i16 %x to <2 x i8>
@@ -33,7 +33,7 @@ define i16 @insert1_v2i8(i16 %x, i8 %y) {
 ; BE-LABEL: @insert1_v2i8(
 ; BE-NEXT:    [[TMP1:%.*]] = and i16 [[X:%.*]], -256
 ; BE-NEXT:    [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i16
-; BE-NEXT:    [[R:%.*]] = or i16 [[TMP1]], [[TMP2]]
+; BE-NEXT:    [[R:%.*]] = or disjoint i16 [[TMP1]], [[TMP2]]
 ; BE-NEXT:    ret i16 [[R]]
 ;
 ; LE-LABEL: @insert1_v2i8(
@@ -61,7 +61,7 @@ define i32 @insert0_v4i8(i32 %x, i8 %y) {
 ; LE-LABEL: @insert0_v4i8(
 ; LE-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -256
 ; LE-NEXT:    [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i32
-; LE-NEXT:    [[R:%.*]] = or i32 [[TMP1]], [[TMP2]]
+; LE-NEXT:    [[R:%.*]] = or disjoint i32 [[TMP1]], [[TMP2]]
 ; LE-NEXT:    ret i32 [[R]]
 ;
   %v = bitcast i32 %x to <4 x i8>
@@ -100,7 +100,7 @@ define i64 @insert0_v4i16(i64 %x, i16 %y) {
 ; LE-LABEL: @insert0_v4i16(
 ; LE-NEXT:    [[TMP1:%.*]] = and i64 [[X:%.*]], -65536
 ; LE-NEXT:    [[TMP2:%.*]] = zext i16 [[Y:%.*]] to i64
-; LE-NEXT:    [[R:%.*]] = or i64 [[TMP1]], [[TMP2]]
+; LE-NEXT:    [[R:%.*]] = or disjoint i64 [[TMP1]], [[TMP2]]
 ; LE-NEXT:    ret i64 [[R]]
 ;
   %v = bitcast i64 %x to <4 x i16>
@@ -131,7 +131,7 @@ define i64 @insert3_v4i16(i64 %x, i16 %y) {
 ; BE-LABEL: @insert3_v4i16(
 ; BE-NEXT:    [[TMP1:%.*]] = and i64 [[X:%.*]], -65536
 ; BE-NEXT:    [[TMP2:%.*]] = zext i16 [[Y:%.*]] to i64
-; BE-NEXT:    [[R:%.*]] = or i64 [[TMP1]], [[TMP2]]
+; BE-NEXT:    [[R:%.*]] = or disjoint i64 [[TMP1]], [[TMP2]]
 ; BE-NEXT:    ret i64 [[R]]
 ;
 ; LE-LABEL: @insert3_v4i16(

llvm/test/Transforms/InstCombine/bitreverse.ll

@@ -243,7 +243,7 @@ define i8 @rev8_mul_and_lshr(i8 %0) {
 ; CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 139536
 ; CHECK-NEXT:    [[TMP5:%.*]] = mul nuw nsw i64 [[TMP2]], 32800
 ; CHECK-NEXT:    [[TMP6:%.*]] = and i64 [[TMP5]], 558144
-; CHECK-NEXT:    [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
+; CHECK-NEXT:    [[TMP7:%.*]] = or disjoint i64 [[TMP4]], [[TMP6]]
 ; CHECK-NEXT:    [[TMP8:%.*]] = mul nuw nsw i64 [[TMP7]], 65793
 ; CHECK-NEXT:    [[TMP9:%.*]] = lshr i64 [[TMP8]], 16
 ; CHECK-NEXT:    [[TMP10:%.*]] = trunc i64 [[TMP9]] to i8

llvm/test/Transforms/InstCombine/bswap.ll

@@ -42,7 +42,7 @@ define i16 @test1_trunc(i32 %i) {
 ; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[I:%.*]], 24
 ; CHECK-NEXT:    [[T3:%.*]] = lshr i32 [[I]], 8
 ; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T3]], 65280
-; CHECK-NEXT:    [[T5:%.*]] = or i32 [[T1]], [[T4]]
+; CHECK-NEXT:    [[T5:%.*]] = or disjoint i32 [[T1]], [[T4]]
 ; CHECK-NEXT:    [[T13:%.*]] = trunc i32 [[T5]] to i16
 ; CHECK-NEXT:    ret i16 [[T13]]
 ;
@@ -59,7 +59,7 @@ define i16 @test1_trunc_extra_use(i32 %i) {
 ; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[I:%.*]], 24
 ; CHECK-NEXT:    [[T3:%.*]] = lshr i32 [[I]], 8
 ; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T3]], 65280
-; CHECK-NEXT:    [[T5:%.*]] = or i32 [[T1]], [[T4]]
+; CHECK-NEXT:    [[T5:%.*]] = or disjoint i32 [[T1]], [[T4]]
 ; CHECK-NEXT:    call void @extra_use(i32 [[T5]])
 ; CHECK-NEXT:    [[T13:%.*]] = trunc i32 [[T5]] to i16
 ; CHECK-NEXT:    ret i16 [[T13]]
@@ -605,7 +605,7 @@ define i64 @bswap_and_mask_1(i64 %0) {
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i64 [[TMP0:%.*]], 56
 ; CHECK-NEXT:    [[TMP3:%.*]] = lshr i64 [[TMP0]], 40
 ; CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 65280
-; CHECK-NEXT:    [[TMP5:%.*]] = or i64 [[TMP4]], [[TMP2]]
+; CHECK-NEXT:    [[TMP5:%.*]] = or disjoint i64 [[TMP4]], [[TMP2]]
 ; CHECK-NEXT:    ret i64 [[TMP5]]
 ;
   %2 = lshr i64 %0, 56
@@ -781,7 +781,7 @@ define i16 @trunc_bswap_i160(ptr %a0) {
 ; CHECK-NEXT:    [[SH_DIFF:%.*]] = lshr i160 [[LOAD]], 120
 ; CHECK-NEXT:    [[TR_SH_DIFF:%.*]] = trunc i160 [[SH_DIFF]] to i16
 ; CHECK-NEXT:    [[SHL:%.*]] = and i16 [[TR_SH_DIFF]], -256
-; CHECK-NEXT:    [[OR:%.*]] = or i16 [[AND1]], [[SHL]]
+; CHECK-NEXT:    [[OR:%.*]] = or disjoint i16 [[AND1]], [[SHL]]
 ; CHECK-NEXT:    ret i16 [[OR]]
 ;
   %load = load i160, ptr %a0, align 4

llvm/test/Transforms/InstCombine/cast-mul-select.ll

@@ -149,7 +149,7 @@ define i32 @eval_sext_multi_use_in_one_inst(i32 %x) {
 ; CHECK-NEXT:    [[T:%.*]] = trunc i32 [[X:%.*]] to i16
 ; CHECK-NEXT:    [[A:%.*]] = and i16 [[T]], 14
 ; CHECK-NEXT:    [[M:%.*]] = mul nuw nsw i16 [[A]], [[A]]
-; CHECK-NEXT:    [[O:%.*]] = or i16 [[M]], -32768
+; CHECK-NEXT:    [[O:%.*]] = or disjoint i16 [[M]], -32768
 ; CHECK-NEXT:    [[R:%.*]] = sext i16 [[O]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
@@ -160,7 +160,7 @@ define i32 @eval_sext_multi_use_in_one_inst(i32 %x) {
 ; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i16 [[A]], metadata [[META77:![0-9]+]], metadata !DIExpression()), !dbg [[DBG82]]
 ; DBGINFO-NEXT:    [[M:%.*]] = mul nuw nsw i16 [[A]], [[A]], !dbg [[DBG83:![0-9]+]]
 ; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i16 [[M]], metadata [[META78:![0-9]+]], metadata !DIExpression()), !dbg [[DBG83]]
-; DBGINFO-NEXT:    [[O:%.*]] = or i16 [[M]], -32768, !dbg [[DBG84:![0-9]+]]
+; DBGINFO-NEXT:    [[O:%.*]] = or disjoint i16 [[M]], -32768, !dbg [[DBG84:![0-9]+]]
 ; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i16 [[O]], metadata [[META79:![0-9]+]], metadata !DIExpression()), !dbg [[DBG84]]
 ; DBGINFO-NEXT:    [[R:%.*]] = sext i16 [[O]] to i32, !dbg [[DBG85:![0-9]+]]
 ; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[R]], metadata [[META80:![0-9]+]], metadata !DIExpression()), !dbg [[DBG85]]

llvm/test/Transforms/InstCombine/cast.ll

@@ -467,7 +467,7 @@ define i16 @test40(i16 %a) {
 ; ALL-LABEL: @test40(
 ; ALL-NEXT:    [[T21:%.*]] = lshr i16 [[A:%.*]], 9
 ; ALL-NEXT:    [[T5:%.*]] = shl i16 [[A]], 8
-; ALL-NEXT:    [[T32:%.*]] = or i16 [[T21]], [[T5]]
+; ALL-NEXT:    [[T32:%.*]] = or disjoint i16 [[T21]], [[T5]]
 ; ALL-NEXT:    ret i16 [[T32]]
 ;
   %t = zext i16 %a to i32
@@ -482,7 +482,7 @@ define <2 x i16> @test40vec(<2 x i16> %a) {
 ; ALL-LABEL: @test40vec(
 ; ALL-NEXT:    [[T21:%.*]] = lshr <2 x i16> [[A:%.*]], <i16 9, i16 9>
 ; ALL-NEXT:    [[T5:%.*]] = shl <2 x i16> [[A]], <i16 8, i16 8>
-; ALL-NEXT:    [[T32:%.*]] = or <2 x i16> [[T21]], [[T5]]
+; ALL-NEXT:    [[T32:%.*]] = or disjoint <2 x i16> [[T21]], [[T5]]
 ; ALL-NEXT:    ret <2 x i16> [[T32]]
 ;
   %t = zext <2 x i16> %a to <2 x i32>
@@ -497,7 +497,7 @@ define <2 x i16> @test40vec_nonuniform(<2 x i16> %a) {
 ; ALL-LABEL: @test40vec_nonuniform(
 ; ALL-NEXT:    [[T21:%.*]] = lshr <2 x i16> [[A:%.*]], <i16 9, i16 10>
 ; ALL-NEXT:    [[T5:%.*]] = shl <2 x i16> [[A]], <i16 8, i16 9>
-; ALL-NEXT:    [[T32:%.*]] = or <2 x i16> [[T21]], [[T5]]
+; ALL-NEXT:    [[T32:%.*]] = or disjoint <2 x i16> [[T21]], [[T5]]
 ; ALL-NEXT:    ret <2 x i16> [[T32]]
 ;
   %t = zext <2 x i16> %a to <2 x i32>
@@ -646,7 +646,7 @@ define i64 @test48(i8 %A1, i8 %a2) {
 ; ALL-LABEL: @test48(
 ; ALL-NEXT:    [[Z2:%.*]] = zext i8 [[A1:%.*]] to i32
 ; ALL-NEXT:    [[C:%.*]] = shl nuw nsw i32 [[Z2]], 8
-; ALL-NEXT:    [[D:%.*]] = or i32 [[C]], [[Z2]]
+; ALL-NEXT:    [[D:%.*]] = or disjoint i32 [[C]], [[Z2]]
 ; ALL-NEXT:    [[E:%.*]] = zext nneg i32 [[D]] to i64
 ; ALL-NEXT:    ret i64 [[E]]
 ;
@@ -690,7 +690,7 @@ define i64 @test51(i64 %A, i1 %cond) {
 ; ALL-NEXT:    [[C:%.*]] = and i64 [[A:%.*]], 4294967294
 ; ALL-NEXT:    [[NOT_COND:%.*]] = xor i1 [[COND:%.*]], true
 ; ALL-NEXT:    [[MASKSEL:%.*]] = zext i1 [[NOT_COND]] to i64
-; ALL-NEXT:    [[E:%.*]] = or i64 [[C]], [[MASKSEL]]
+; ALL-NEXT:    [[E:%.*]] = or disjoint i64 [[C]], [[MASKSEL]]
 ; ALL-NEXT:    [[SEXT:%.*]] = shl nuw i64 [[E]], 32
 ; ALL-NEXT:    [[F:%.*]] = ashr exact i64 [[SEXT]], 32
 ; ALL-NEXT:    ret i64 [[F]]
@@ -707,7 +707,7 @@ define i32 @test52(i64 %A) {
 ; ALL-LABEL: @test52(
 ; ALL-NEXT:    [[B:%.*]] = trunc i64 [[A:%.*]] to i32
 ; ALL-NEXT:    [[C:%.*]] = and i32 [[B]], 7224
-; ALL-NEXT:    [[D:%.*]] = or i32 [[C]], 32962
+; ALL-NEXT:    [[D:%.*]] = or disjoint i32 [[C]], 32962
 ; ALL-NEXT:    ret i32 [[D]]
 ;
   %B = trunc i64 %A to i16
@@ -720,7 +720,7 @@ define i32 @test52(i64 %A) {
 define i64 @test53(i32 %A) {
 ; ALL-LABEL: @test53(
 ; ALL-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], 7224
-; ALL-NEXT:    [[TMP2:%.*]] = or i32 [[TMP1]], 32962
+; ALL-NEXT:    [[TMP2:%.*]] = or disjoint i32 [[TMP1]], 32962
 ; ALL-NEXT:    [[D:%.*]] = zext nneg i32 [[TMP2]] to i64
 ; ALL-NEXT:    ret i64 [[D]]
 ;
@@ -735,7 +735,7 @@ define i32 @test54(i64 %A) {
 ; ALL-LABEL: @test54(
 ; ALL-NEXT:    [[B:%.*]] = trunc i64 [[A:%.*]] to i32
 ; ALL-NEXT:    [[C:%.*]] = and i32 [[B]], 7224
-; ALL-NEXT:    [[D:%.*]] = or i32 [[C]], -32574
+; ALL-NEXT:    [[D:%.*]] = or disjoint i32 [[C]], -32574
 ; ALL-NEXT:    ret i32 [[D]]
 ;
   %B = trunc i64 %A to i16
@@ -749,7 +749,7 @@ define i64 @test55(i32 %A) {
 ; ALL-LABEL: @test55(
 ; ALL-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], 7224
 ; ALL-NEXT:    [[C:%.*]] = zext nneg i32 [[TMP1]] to i64
-; ALL-NEXT:    [[D:%.*]] = or i64 [[C]], -32574
+; ALL-NEXT:    [[D:%.*]] = or disjoint i64 [[C]], -32574
 ; ALL-NEXT:    ret i64 [[D]]
 ;
   %B = trunc i32 %A to i16
@@ -814,7 +814,7 @@ define i64 @test58(i64 %A) {
 ; ALL-LABEL: @test58(
 ; ALL-NEXT:    [[C:%.*]] = lshr i64 [[A:%.*]], 8
 ; ALL-NEXT:    [[D:%.*]] = and i64 [[C]], 16777087
-; ALL-NEXT:    [[E:%.*]] = or i64 [[D]], 128
+; ALL-NEXT:    [[E:%.*]] = or disjoint i64 [[D]], 128
 ; ALL-NEXT:    ret i64 [[E]]
 ;
   %B = trunc i64 %A to i32
@@ -832,7 +832,7 @@ define i64 @test59(i8 %A, i8 %B) {
 ; ALL-NEXT:    [[E:%.*]] = and i64 [[D]], 48
 ; ALL-NEXT:    [[TMP1:%.*]] = lshr i8 [[B:%.*]], 4
 ; ALL-NEXT:    [[G:%.*]] = zext nneg i8 [[TMP1]] to i64
-; ALL-NEXT:    [[H:%.*]] = or i64 [[E]], [[G]]
+; ALL-NEXT:    [[H:%.*]] = or disjoint i64 [[E]], [[G]]
 ; ALL-NEXT:    ret i64 [[H]]
 ;
   %C = zext i8 %A to i32
@@ -2139,7 +2139,7 @@ define i32 @test95(i32 %x) {
 ; ALL-LABEL: @test95(
 ; ALL-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 6
 ; ALL-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 2
-; ALL-NEXT:    [[TMP3:%.*]] = or i32 [[TMP2]], 40
+; ALL-NEXT:    [[TMP3:%.*]] = or disjoint i32 [[TMP2]], 40
 ; ALL-NEXT:    ret i32 [[TMP3]]
 ;
   %1 = trunc i32 %x to i8

llvm/test/Transforms/InstCombine/free-inversion.ll

@@ -526,7 +526,7 @@ define i8 @lshr_not_nneg(i8 %x, i8 %y) {
 define i8 @lshr_not_nneg2(i8 %x) {
 ; CHECK-LABEL: @lshr_not_nneg2(
 ; CHECK-NEXT:    [[SHR:%.*]] = lshr i8 [[X:%.*]], 1
-; CHECK-NEXT:    [[SHR_NOT1:%.*]] = or i8 [[SHR]], -128
+; CHECK-NEXT:    [[SHR_NOT1:%.*]] = or disjoint i8 [[SHR]], -128
 ; CHECK-NEXT:    ret i8 [[SHR_NOT1]]
 ;
   %x.not = xor i8 %x, -1