[RISCV] Run mem2reg on the scalar C builtin tests to remove allocas a…

…nd simplify checks. NFC As requested on D155647.
llvm · Jul 19, 2023 · 7fb0f4a · 7fb0f4a
1 parent d015018
commit 7fb0f4a
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Showing 17 changed files with 137 additions and 372 deletions.
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
@@ -1,27 +1,22 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv32 -target-feature +xtheadbb -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV32XTHEADBB
 
 // RV32XTHEADBB-LABEL: @clz_32(
 // RV32XTHEADBB-NEXT:  entry:
-// RV32XTHEADBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV32XTHEADBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV32XTHEADBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV32XTHEADBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
-// RV32XTHEADBB-NEXT:    ret i32 [[TMP1]]
+// RV32XTHEADBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[A:%.*]], i1 false)
+// RV32XTHEADBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
 // RV32XTHEADBB-LABEL: @clo_32(
 // RV32XTHEADBB-NEXT:  entry:
-// RV32XTHEADBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV32XTHEADBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV32XTHEADBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV32XTHEADBB-NEXT:    [[NOT:%.*]] = xor i32 [[TMP0]], -1
-// RV32XTHEADBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[NOT]], i1 false)
-// RV32XTHEADBB-NEXT:    ret i32 [[TMP1]]
+// RV32XTHEADBB-NEXT:    [[NOT:%.*]] = xor i32 [[A:%.*]], -1
+// RV32XTHEADBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[NOT]], i1 false)
+// RV32XTHEADBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int clo_32(unsigned int a) {
   return __builtin_riscv_clz_32(~a);

diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
@@ -1,16 +1,14 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv32 -target-feature +zbkb -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV32ZBKB
 
 #include <stdint.h>
 
 // RV32ZBKB-LABEL: @brev8(
 // RV32ZBKB-NEXT:  entry:
-// RV32ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBKB-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
-// RV32ZBKB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZBKB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[TMP0]])
-// RV32ZBKB-NEXT:    ret i32 [[TMP1]]
+// RV32ZBKB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[RS1:%.*]])
+// RV32ZBKB-NEXT:    ret i32 [[TMP0]]
 //
 uint32_t brev8(uint32_t rs1)
 {
@@ -19,11 +17,8 @@ uint32_t brev8(uint32_t rs1)
 
 // RV32ZBKB-LABEL: @zip(
 // RV32ZBKB-NEXT:  entry:
-// RV32ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBKB-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
-// RV32ZBKB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZBKB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.zip.i32(i32 [[TMP0]])
-// RV32ZBKB-NEXT:    ret i32 [[TMP1]]
+// RV32ZBKB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.zip.i32(i32 [[RS1:%.*]])
+// RV32ZBKB-NEXT:    ret i32 [[TMP0]]
 //
 uint32_t zip(uint32_t rs1)
 {
@@ -32,11 +27,8 @@ uint32_t zip(uint32_t rs1)
 
 // RV32ZBKB-LABEL: @unzip(
 // RV32ZBKB-NEXT:  entry:
-// RV32ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBKB-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
-// RV32ZBKB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZBKB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.unzip.i32(i32 [[TMP0]])
-// RV32ZBKB-NEXT:    ret i32 [[TMP1]]
+// RV32ZBKB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.unzip.i32(i32 [[RS1:%.*]])
+// RV32ZBKB-NEXT:    ret i32 [[TMP0]]
 //
 uint32_t unzip(uint32_t rs1)
 {

diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
@@ -1,34 +1,23 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv32 -target-feature +zbkc -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV32ZBKC
 
 #include <stdint.h>
 
 // RV32ZBKC-LABEL: @clmul_32(
 // RV32ZBKC-NEXT:  entry:
-// RV32ZBKC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBKC-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBKC-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV32ZBKC-NEXT:    store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
-// RV32ZBKC-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV32ZBKC-NEXT:    [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
-// RV32ZBKC-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
-// RV32ZBKC-NEXT:    ret i32 [[TMP2]]
+// RV32ZBKC-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+// RV32ZBKC-NEXT:    ret i32 [[TMP0]]
 //
 uint32_t clmul_32(uint32_t a, uint32_t b) {
   return __builtin_riscv_clmul_32(a, b);
 }
 
 // RV32ZBKC-LABEL: @clmulh_32(
 // RV32ZBKC-NEXT:  entry:
-// RV32ZBKC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBKC-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBKC-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV32ZBKC-NEXT:    store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
-// RV32ZBKC-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV32ZBKC-NEXT:    [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
-// RV32ZBKC-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[TMP0]], i32 [[TMP1]])
-// RV32ZBKC-NEXT:    ret i32 [[TMP2]]
+// RV32ZBKC-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+// RV32ZBKC-NEXT:    ret i32 [[TMP0]]
 //
 uint32_t clmulh_32(uint32_t a, uint32_t b) {
   return __builtin_riscv_clmulh_32(a, b);

diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
@@ -1,19 +1,14 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv32 -target-feature +zbkx -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV32ZBKX
 
 #include <stdint.h>
 
 // RV32ZBKX-LABEL: @xperm8(
 // RV32ZBKX-NEXT:  entry:
-// RV32ZBKX-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBKX-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBKX-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
-// RV32ZBKX-NEXT:    store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
-// RV32ZBKX-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZBKX-NEXT:    [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
-// RV32ZBKX-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.xperm8.i32(i32 [[TMP0]], i32 [[TMP1]])
-// RV32ZBKX-NEXT:    ret i32 [[TMP2]]
+// RV32ZBKX-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.xperm8.i32(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
+// RV32ZBKX-NEXT:    ret i32 [[TMP0]]
 //
 uint32_t xperm8(uint32_t rs1, uint32_t rs2)
 {
@@ -22,14 +17,8 @@ uint32_t xperm8(uint32_t rs1, uint32_t rs2)
 
 // RV32ZBKX-LABEL: @xperm4(
 // RV32ZBKX-NEXT:  entry:
-// RV32ZBKX-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBKX-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBKX-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
-// RV32ZBKX-NEXT:    store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
-// RV32ZBKX-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZBKX-NEXT:    [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
-// RV32ZBKX-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.xperm4.i32(i32 [[TMP0]], i32 [[TMP1]])
-// RV32ZBKX-NEXT:    ret i32 [[TMP2]]
+// RV32ZBKX-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.xperm4.i32(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
+// RV32ZBKX-NEXT:    ret i32 [[TMP0]]
 //
 uint32_t xperm4(uint32_t rs1, uint32_t rs2)
 {

diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
@@ -1,39 +1,31 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadbb -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV64XTHEADBB
 
 // RV64XTHEADBB-LABEL: @clz_32(
 // RV64XTHEADBB-NEXT:  entry:
-// RV64XTHEADBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV64XTHEADBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV64XTHEADBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV64XTHEADBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
-// RV64XTHEADBB-NEXT:    ret i32 [[TMP1]]
+// RV64XTHEADBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[A:%.*]], i1 false)
+// RV64XTHEADBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
 // RV64XTHEADBB-LABEL: @clo_32(
 // RV64XTHEADBB-NEXT:  entry:
-// RV64XTHEADBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV64XTHEADBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV64XTHEADBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV64XTHEADBB-NEXT:    [[NOT:%.*]] = xor i32 [[TMP0]], -1
-// RV64XTHEADBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[NOT]], i1 false)
-// RV64XTHEADBB-NEXT:    ret i32 [[TMP1]]
+// RV64XTHEADBB-NEXT:    [[NOT:%.*]] = xor i32 [[A:%.*]], -1
+// RV64XTHEADBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[NOT]], i1 false)
+// RV64XTHEADBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int clo_32(unsigned int a) {
   return __builtin_riscv_clz_32(~a);
 }
 
 // RV64XTHEADBB-LABEL: @clz_64(
 // RV64XTHEADBB-NEXT:  entry:
-// RV64XTHEADBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
-// RV64XTHEADBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
-// RV64XTHEADBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
-// RV64XTHEADBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
-// RV64XTHEADBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64XTHEADBB-NEXT:    [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[A:%.*]], i1 false)
+// RV64XTHEADBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i32
 // RV64XTHEADBB-NEXT:    ret i32 [[CAST]]
 //
 unsigned int clz_64(unsigned long a) {
@@ -42,12 +34,9 @@ unsigned int clz_64(unsigned long a) {
 
 // RV64XTHEADBB-LABEL: @clo_64(
 // RV64XTHEADBB-NEXT:  entry:
-// RV64XTHEADBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
-// RV64XTHEADBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
-// RV64XTHEADBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
-// RV64XTHEADBB-NEXT:    [[NOT:%.*]] = xor i64 [[TMP0]], -1
-// RV64XTHEADBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[NOT]], i1 false)
-// RV64XTHEADBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64XTHEADBB-NEXT:    [[NOT:%.*]] = xor i64 [[A:%.*]], -1
+// RV64XTHEADBB-NEXT:    [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[NOT]], i1 false)
+// RV64XTHEADBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i32
 // RV64XTHEADBB-NEXT:    ret i32 [[CAST]]
 //
 unsigned int clo_64(unsigned long a) {

diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
@@ -1,16 +1,14 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV64ZBKB
 
 #include <stdint.h>
 
 // RV64ZBKB-LABEL: @brev8_32(
 // RV64ZBKB-NEXT:  entry:
-// RV64ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
-// RV64ZBKB-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
-// RV64ZBKB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV64ZBKB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[TMP0]])
-// RV64ZBKB-NEXT:    ret i32 [[TMP1]]
+// RV64ZBKB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[RS1:%.*]])
+// RV64ZBKB-NEXT:    ret i32 [[TMP0]]
 //
 uint32_t brev8_32(uint32_t rs1)
 {
@@ -19,11 +17,8 @@ uint32_t brev8_32(uint32_t rs1)
 
 // RV64ZBKB-LABEL: @brev8_64(
 // RV64ZBKB-NEXT:  entry:
-// RV64ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBKB-NEXT:    store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
-// RV64ZBKB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
-// RV64ZBKB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.brev8.i64(i64 [[TMP0]])
-// RV64ZBKB-NEXT:    ret i64 [[TMP1]]
+// RV64ZBKB-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.brev8.i64(i64 [[RS1:%.*]])
+// RV64ZBKB-NEXT:    ret i64 [[TMP0]]
 //
 uint64_t brev8_64(uint64_t rs1)
 {

diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
@@ -1,49 +1,32 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbkc -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV64ZBKC
 
 #include <stdint.h>
 
 // RV64ZBKC-LABEL: @clmul_64(
 // RV64ZBKC-NEXT:  entry:
-// RV64ZBKC-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBKC-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBKC-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
-// RV64ZBKC-NEXT:    store i64 [[B:%.*]], ptr [[B_ADDR]], align 8
-// RV64ZBKC-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
-// RV64ZBKC-NEXT:    [[TMP1:%.*]] = load i64, ptr [[B_ADDR]], align 8
-// RV64ZBKC-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[TMP0]], i64 [[TMP1]])
-// RV64ZBKC-NEXT:    ret i64 [[TMP2]]
+// RV64ZBKC-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[A:%.*]], i64 [[B:%.*]])
+// RV64ZBKC-NEXT:    ret i64 [[TMP0]]
 //
 uint64_t clmul_64(uint64_t a, uint64_t b) {
   return __builtin_riscv_clmul_64(a, b);
 }
 
 // RV64ZBKC-LABEL: @clmulh_64(
 // RV64ZBKC-NEXT:  entry:
-// RV64ZBKC-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBKC-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBKC-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
-// RV64ZBKC-NEXT:    store i64 [[B:%.*]], ptr [[B_ADDR]], align 8
-// RV64ZBKC-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
-// RV64ZBKC-NEXT:    [[TMP1:%.*]] = load i64, ptr [[B_ADDR]], align 8
-// RV64ZBKC-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[TMP0]], i64 [[TMP1]])
-// RV64ZBKC-NEXT:    ret i64 [[TMP2]]
+// RV64ZBKC-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[A:%.*]], i64 [[B:%.*]])
+// RV64ZBKC-NEXT:    ret i64 [[TMP0]]
 //
 uint64_t clmulh_64(uint64_t a, uint64_t b) {
   return __builtin_riscv_clmulh_64(a, b);
 }
 
 // RV64ZBKC-LABEL: @clmul_32(
 // RV64ZBKC-NEXT:  entry:
-// RV64ZBKC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV64ZBKC-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
-// RV64ZBKC-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV64ZBKC-NEXT:    store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
-// RV64ZBKC-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV64ZBKC-NEXT:    [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
-// RV64ZBKC-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
-// RV64ZBKC-NEXT:    ret i32 [[TMP2]]
+// RV64ZBKC-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+// RV64ZBKC-NEXT:    ret i32 [[TMP0]]
 //
 uint32_t clmul_32(uint32_t a, uint32_t b) {
   return __builtin_riscv_clmul_32(a, b);

diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
@@ -1,19 +1,14 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbkx -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV64ZBKX
 
 #include <stdint.h>
 
 // RV64ZBKX-LABEL: @xperm8(
 // RV64ZBKX-NEXT:  entry:
-// RV64ZBKX-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBKX-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBKX-NEXT:    store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
-// RV64ZBKX-NEXT:    store i64 [[RS2:%.*]], ptr [[RS2_ADDR]], align 8
-// RV64ZBKX-NEXT:    [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
-// RV64ZBKX-NEXT:    [[TMP1:%.*]] = load i64, ptr [[RS2_ADDR]], align 8
-// RV64ZBKX-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.xperm8.i64(i64 [[TMP0]], i64 [[TMP1]])
-// RV64ZBKX-NEXT:    ret i64 [[TMP2]]
+// RV64ZBKX-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.xperm8.i64(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
+// RV64ZBKX-NEXT:    ret i64 [[TMP0]]
 //
 uint64_t xperm8(uint64_t rs1, uint64_t rs2)
 {
@@ -22,14 +17,8 @@ uint64_t xperm8(uint64_t rs1, uint64_t rs2)
 
 // RV64ZBKX-LABEL: @xperm4(
 // RV64ZBKX-NEXT:  entry:
-// RV64ZBKX-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBKX-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBKX-NEXT:    store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
-// RV64ZBKX-NEXT:    store i64 [[RS2:%.*]], ptr [[RS2_ADDR]], align 8
-// RV64ZBKX-NEXT:    [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
-// RV64ZBKX-NEXT:    [[TMP1:%.*]] = load i64, ptr [[RS2_ADDR]], align 8
-// RV64ZBKX-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.xperm4.i64(i64 [[TMP0]], i64 [[TMP1]])
-// RV64ZBKX-NEXT:    ret i64 [[TMP2]]
+// RV64ZBKX-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.xperm4.i64(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
+// RV64ZBKX-NEXT:    ret i64 [[TMP0]]
 //
 uint64_t xperm4(uint64_t rs1, uint64_t rs2)
 {

diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
@@ -1,34 +1,23 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv32 -target-feature +zknd -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV32ZKND
 
 #include <stdint.h>
 
 // RV32ZKND-LABEL: @aes32dsi(
 // RV32ZKND-NEXT:  entry:
-// RV32ZKND-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
-// RV32ZKND-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
-// RV32ZKND-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
-// RV32ZKND-NEXT:    store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
-// RV32ZKND-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZKND-NEXT:    [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
-// RV32ZKND-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.aes32dsi(i32 [[TMP0]], i32 [[TMP1]], i32 3)
-// RV32ZKND-NEXT:    ret i32 [[TMP2]]
+// RV32ZKND-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.aes32dsi(i32 [[RS1:%.*]], i32 [[RS2:%.*]], i32 3)
+// RV32ZKND-NEXT:    ret i32 [[TMP0]]
 //
 uint32_t aes32dsi(uint32_t rs1, uint32_t rs2) {
   return __builtin_riscv_aes32dsi(rs1, rs2, 3);
 }
 
 // RV32ZKND-LABEL: @aes32dsmi(
 // RV32ZKND-NEXT:  entry:
-// RV32ZKND-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
-// RV32ZKND-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
-// RV32ZKND-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
-// RV32ZKND-NEXT:    store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
-// RV32ZKND-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZKND-NEXT:    [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
-// RV32ZKND-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.aes32dsmi(i32 [[TMP0]], i32 [[TMP1]], i32 3)
-// RV32ZKND-NEXT:    ret i32 [[TMP2]]
+// RV32ZKND-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.aes32dsmi(i32 [[RS1:%.*]], i32 [[RS2:%.*]], i32 3)
+// RV32ZKND-NEXT:    ret i32 [[TMP0]]
 //
 uint32_t aes32dsmi(uint32_t rs1, uint32_t rs2) {
   return __builtin_riscv_aes32dsmi(rs1, rs2, 3);