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[llvm-exegesis][NFC] Refactor X86 tests fixtures into a base class.
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Reviewers: gchatelet, a.sidorin

Subscribers: tschuett, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68262

llvm-svn: 373313
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legrosbuffle committed Oct 1, 2019
1 parent cf62871 commit 8109901
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Showing 6 changed files with 71 additions and 101 deletions.
36 changes: 5 additions & 31 deletions llvm/unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp
Expand Up @@ -12,6 +12,7 @@
#include <cassert>
#include <memory>

#include "TestBase.h"
#include "X86InstrInfo.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
Expand All @@ -22,37 +23,10 @@ namespace llvm {
namespace exegesis {
namespace {

class RegisterAliasingTest : public ::testing::Test {
protected:
RegisterAliasingTest() {
const std::string TT = "x86_64-unknown-linux";
std::string error;
const llvm::Target *const TheTarget =
llvm::TargetRegistry::lookupTarget(TT, error);
if (!TheTarget) {
llvm::errs() << error << "\n";
return;
}
MCRegInfo.reset(TheTarget->createMCRegInfo(TT));
}

static void SetUpTestCase() {
LLVMInitializeX86TargetInfo();
LLVMInitializeX86Target();
LLVMInitializeX86TargetMC();
}

const llvm::MCRegisterInfo &getMCRegInfo() {
assert(MCRegInfo);
return *MCRegInfo;
}

private:
std::unique_ptr<const llvm::MCRegisterInfo> MCRegInfo;
};
class RegisterAliasingTest : public X86TestBase {};

TEST_F(RegisterAliasingTest, TrackSimpleRegister) {
const auto &RegInfo = getMCRegInfo();
const auto &RegInfo = State.getRegInfo();
const RegisterAliasingTracker tracker(RegInfo, llvm::X86::EAX);
std::set<llvm::MCPhysReg> ActualAliasedRegisters;
for (unsigned I : tracker.aliasedBits().set_bits())
Expand All @@ -69,7 +43,7 @@ TEST_F(RegisterAliasingTest, TrackSimpleRegister) {
TEST_F(RegisterAliasingTest, TrackRegisterClass) {
// The alias bits for GR8_ABCD_LRegClassID are the union of the alias bits for
// AL, BL, CL and DL.
const auto &RegInfo = getMCRegInfo();
const auto &RegInfo = State.getRegInfo();
const llvm::BitVector NoReservedReg(RegInfo.getNumRegs());

const RegisterAliasingTracker RegClassTracker(
Expand All @@ -87,7 +61,7 @@ TEST_F(RegisterAliasingTest, TrackRegisterClass) {

TEST_F(RegisterAliasingTest, TrackRegisterClassCache) {
// Fetching twice the same tracker yields the same pointers.
const auto &RegInfo = getMCRegInfo();
const auto &RegInfo = State.getRegInfo();
const llvm::BitVector NoReservedReg(RegInfo.getNumRegs());
RegisterAliasingTrackerCache Cache(RegInfo, NoReservedReg);
ASSERT_THAT(&Cache.getRegister(llvm::X86::AX),
Expand Down
Expand Up @@ -11,6 +11,7 @@
#include <cassert>
#include <memory>

#include "TestBase.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
Expand All @@ -23,21 +24,11 @@ namespace {
using testing::Pair;
using testing::UnorderedElementsAre;

class SchedClassResolutionTest : public ::testing::Test {
class SchedClassResolutionTest : public X86TestBase {
protected:
SchedClassResolutionTest() {
const std::string TT = "x86_64-unknown-linux";
std::string error;
const llvm::Target *const TheTarget =
llvm::TargetRegistry::lookupTarget(TT, error);
if (!TheTarget) {
llvm::errs() << error << "\n";
return;
}
STI.reset(TheTarget->createMCSubtargetInfo(TT, "haswell", ""));

SchedClassResolutionTest() : STI(State.getSubtargetInfo()) {
// Compute the ProxResIdx of ports uses in tests.
const auto &SM = STI->getSchedModel();
const auto &SM = STI.getSchedModel();
for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
const std::string Name = SM.getProcResource(I)->Name;
if (Name == "HWPort0") {
Expand All @@ -62,14 +53,8 @@ class SchedClassResolutionTest : public ::testing::Test {
EXPECT_NE(P0156Idx, 0);
}

static void SetUpTestCase() {
LLVMInitializeX86TargetInfo();
LLVMInitializeX86Target();
LLVMInitializeX86TargetMC();
}

protected:
std::unique_ptr<const llvm::MCSubtargetInfo> STI;
const llvm::MCSubtargetInfo &STI;
uint16_t P0Idx = 0;
uint16_t P1Idx = 0;
uint16_t P5Idx = 0;
Expand All @@ -80,20 +65,20 @@ class SchedClassResolutionTest : public ::testing::Test {

TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P0) {
const auto Pressure =
computeIdealizedProcResPressure(STI->getSchedModel(), {{P0Idx, 2}});
computeIdealizedProcResPressure(STI.getSchedModel(), {{P0Idx, 2}});
EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(P0Idx, 2.0)));
}

TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05) {
const auto Pressure =
computeIdealizedProcResPressure(STI->getSchedModel(), {{P05Idx, 2}});
computeIdealizedProcResPressure(STI.getSchedModel(), {{P05Idx, 2}});
EXPECT_THAT(Pressure,
UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P5Idx, 1.0)));
}

TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05_2P0156) {
const auto Pressure = computeIdealizedProcResPressure(
STI->getSchedModel(), {{P05Idx, 2}, {P0156Idx, 2}});
STI.getSchedModel(), {{P05Idx, 2}, {P0156Idx, 2}});
EXPECT_THAT(Pressure,
UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P1Idx, 1.0),
Pair(P5Idx, 1.0), Pair(P6Idx, 1.0)));
Expand All @@ -102,7 +87,7 @@ TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05_2P0156) {
TEST_F(SchedClassResolutionTest,
ComputeIdealizedProcResPressure_1P1_1P05_2P0156) {
const auto Pressure = computeIdealizedProcResPressure(
STI->getSchedModel(), {{P1Idx, 1}, {P05Idx, 1}, {P0156Idx, 2}});
STI.getSchedModel(), {{P1Idx, 1}, {P05Idx, 1}, {P0156Idx, 2}});
EXPECT_THAT(Pressure,
UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P1Idx, 1.0),
Pair(P5Idx, 1.0), Pair(P6Idx, 1.0)));
Expand Down
16 changes: 2 additions & 14 deletions llvm/unittests/tools/llvm-exegesis/X86/SnippetFileTest.cpp
Expand Up @@ -9,6 +9,7 @@
#include "SnippetFile.h"

#include "LlvmState.h"
#include "TestBase.h"
#include "X86InstrInfo.h"
#include "llvm/Support/Error.h"
#include "llvm/Support/FileSystem.h"
Expand All @@ -33,19 +34,8 @@ using testing::Field;
using testing::Property;
using testing::SizeIs;

class X86SnippetFileTest : public ::testing::Test {
class X86SnippetFileTest : public X86TestBase {
protected:
X86SnippetFileTest() : State("x86_64-unknown-linux", "haswell") {}

static void SetUpTestCase() {
LLVMInitializeX86TargetInfo();
LLVMInitializeX86TargetMC();
LLVMInitializeX86Target();
LLVMInitializeX86AsmPrinter();
LLVMInitializeX86AsmParser();
InitializeX86ExegesisTarget();
}

Expected<std::vector<BenchmarkCode>> TestCommon(StringRef Contents) {
SmallString<64> Filename;
std::error_code EC;
Expand All @@ -60,8 +50,6 @@ class X86SnippetFileTest : public ::testing::Test {
}
return readSnippets(State, Filename);
}

const LLVMState State;
};

// FIXME: Refactor these to ../Common/Matchers.h
Expand Down
29 changes: 9 additions & 20 deletions llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
Expand Up @@ -11,6 +11,7 @@
#include "LlvmState.h"
#include "MCInstrDescView.h"
#include "RegisterAliasing.h"
#include "TestBase.h"
#include "Uops.h"
#include "X86InstrInfo.h"

Expand All @@ -34,23 +35,11 @@ using testing::UnorderedElementsAre;
MATCHER(IsInvalid, "") { return !arg.isValid(); }
MATCHER(IsReg, "") { return arg.isReg(); }

class X86SnippetGeneratorTest : public ::testing::Test {
class X86SnippetGeneratorTest : public X86TestBase {
protected:
X86SnippetGeneratorTest()
: State("x86_64-unknown-linux", "haswell"),
MCInstrInfo(State.getInstrInfo()), MCRegisterInfo(State.getRegInfo()) {}

static void SetUpTestCase() {
LLVMInitializeX86TargetInfo();
LLVMInitializeX86TargetMC();
LLVMInitializeX86Target();
LLVMInitializeX86AsmPrinter();
InitializeX86ExegesisTarget();
}
X86SnippetGeneratorTest() : InstrInfo(State.getInstrInfo()) {}

const LLVMState State;
const llvm::MCInstrInfo &MCInstrInfo;
const llvm::MCRegisterInfo &MCRegisterInfo;
const llvm::MCInstrInfo &InstrInfo;
};

template <typename SnippetGeneratorT>
Expand Down Expand Up @@ -86,10 +75,10 @@ TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) {
// - hasAliasingImplicitRegisters (execution is always serial)
// - hasAliasingRegisters
const unsigned Opcode = llvm::X86::ADC16i16;
EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::AX);
EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[1], llvm::X86::EFLAGS);
EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitUses()[0], llvm::X86::AX);
EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitUses()[1], llvm::X86::EFLAGS);
EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::AX);
EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[1], llvm::X86::EFLAGS);
EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[0], llvm::X86::AX);
EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[1], llvm::X86::EFLAGS);
const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
ASSERT_THAT(CodeTemplates, SizeIs(1));
const auto &CT = CodeTemplates[0];
Expand All @@ -112,7 +101,7 @@ TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
// - hasTiedRegisters (execution is always serial)
// - hasAliasingRegisters
const unsigned Opcode = llvm::X86::ADD16ri;
EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::EFLAGS);
EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::EFLAGS);
const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
ASSERT_THAT(CodeTemplates, SizeIs(1));
const auto &CT = CodeTemplates[0];
Expand Down
14 changes: 2 additions & 12 deletions llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp
Expand Up @@ -11,6 +11,7 @@
#include "LlvmState.h"
#include "MCInstrDescView.h"
#include "RegisterAliasing.h"
#include "TestBase.h"
#include "Uops.h"
#include "X86InstrInfo.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
Expand All @@ -28,18 +29,8 @@ using testing::Field;
using testing::Property;
using testing::UnorderedElementsAre;

class X86SnippetRepetitorTest : public ::testing::Test {
class X86SnippetRepetitorTest : public X86TestBase {
protected:
X86SnippetRepetitorTest() : State("x86_64-unknown-linux", "haswell") {}

static void SetUpTestCase() {
LLVMInitializeX86TargetInfo();
LLVMInitializeX86TargetMC();
LLVMInitializeX86Target();
LLVMInitializeX86AsmPrinter();
InitializeX86ExegesisTarget();
}

void SetUp() {
TM = State.createTargetMachine();
Context = std::make_unique<LLVMContext>();
Expand All @@ -60,7 +51,6 @@ class X86SnippetRepetitorTest : public ::testing::Test {

static constexpr const unsigned kMinInstructions = 3;

const LLVMState State;
std::unique_ptr<LLVMTargetMachine> TM;
std::unique_ptr<LLVMContext> Context;
std::unique_ptr<Module> Mod;
Expand Down
44 changes: 44 additions & 0 deletions llvm/unittests/tools/llvm-exegesis/X86/TestBase.h
@@ -0,0 +1,44 @@
//===-- TestBase.cpp --------------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// Test fixture common to all X86 tests.
//===----------------------------------------------------------------------===//

#ifndef LLVM_UNITTESTS_TOOLS_LLVMEXEGESIS_X86_TESTBASE_H
#define LLVM_UNITTESTS_TOOLS_LLVMEXEGESIS_X86_TESTBASE_H

#include "LlvmState.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"

namespace llvm {
namespace exegesis {

void InitializeX86ExegesisTarget();

class X86TestBase : public ::testing::Test {
protected:
X86TestBase() : State("x86_64-unknown-linux", "haswell") {}

static void SetUpTestCase() {
LLVMInitializeX86TargetInfo();
LLVMInitializeX86TargetMC();
LLVMInitializeX86Target();
LLVMInitializeX86AsmPrinter();
LLVMInitializeX86AsmParser();
InitializeX86ExegesisTarget();
}

const LLVMState State;
};

} // namespace exegesis
} // namespace llvm

#endif

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