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[ARM][THUMB2] Allow emitting T3 types of add and sub
Summary: This patch allows to emit thumb2 add and sub instructions with 12 bit immediates in the emitT2RegPlusImmediate function. - Splitting parts of the D70680 Reviewers: eli.friedman, olista01, efriedma Reviewed By: efriedma Subscribers: efriedma, kristof.beyls, hiraditya, dmgreen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71361
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Diogo Sampaio
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Dec 30, 2019
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--- | | ||
; RUN: llc --run-pass=prologepilog -o - %s | FileCheck %s | ||
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 | ||
; CHECK-NEXT: $sp = frame-setup t2SUBri12 killed $sp, 4008, 14, $noreg | ||
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" | ||
target triple = "thumbv7-none-none-eabi" | ||
define void @foo() #0 { | ||
entry: | ||
%v = alloca [4000 x i8], align 1 | ||
%s = alloca i8*, align 4 | ||
%0 = bitcast [4000 x i8]* %v to i8* | ||
store i8* %0, i8** %s, align 4 | ||
%1 = load i8*, i8** %s, align 4 | ||
call void @bar(i8* %1) | ||
ret void | ||
} | ||
declare void @bar(i8*) #1 | ||
; Function Attrs: nounwind | ||
declare void @llvm.stackprotector(i8*, i8**) #2 | ||
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attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv7-a,+d32,+dsp,+fp64,+fpregs,+neon,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp" "unsafe-fp-math"="false" "use-soft-float"="false" } | ||
attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv7-a,+d32,+dsp,+fp64,+fpregs,+neon,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp" "unsafe-fp-math"="false" "use-soft-float"="false" } | ||
attributes #2 = { nounwind } | ||
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!llvm.module.flags = !{!0, !1} | ||
!llvm.ident = !{!2} | ||
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!0 = !{i32 1, !"wchar_size", i32 4} | ||
!1 = !{i32 1, !"min_enum_size", i32 4} | ||
!2 = !{!"clang version 10.0.0 (git@github.com:llvm/llvm-project.git ee219345881bdf2c144d40731f055e7b36bc8bce)"} | ||
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... | ||
--- | ||
name: foo | ||
alignment: 2 | ||
exposesReturnsTwice: false | ||
legalized: false | ||
regBankSelected: false | ||
selected: false | ||
failedISel: false | ||
tracksRegLiveness: true | ||
hasWinCFI: false | ||
registers: [] | ||
liveins: [] | ||
frameInfo: | ||
isFrameAddressTaken: false | ||
isReturnAddressTaken: false | ||
hasStackMap: false | ||
hasPatchPoint: false | ||
stackSize: 0 | ||
offsetAdjustment: 0 | ||
maxAlignment: 4 | ||
adjustsStack: true | ||
hasCalls: true | ||
stackProtector: '' | ||
maxCallFrameSize: 0 | ||
cvBytesOfCalleeSavedRegisters: 0 | ||
hasOpaqueSPAdjustment: false | ||
hasVAStart: false | ||
hasMustTailInVarArgFunc: false | ||
localFrameSize: 4004 | ||
savePoint: '' | ||
restorePoint: '' | ||
fixedStack: [] | ||
stack: | ||
- { id: 0, name: v, type: default, offset: 0, size: 4000, alignment: 1, | ||
stack-id: default, callee-saved-register: '', callee-saved-restored: true, | ||
local-offset: -4000, debug-info-variable: '', debug-info-expression: '', | ||
debug-info-location: '' } | ||
- { id: 1, name: s, type: default, offset: 0, size: 4, alignment: 4, | ||
stack-id: default, callee-saved-register: '', callee-saved-restored: true, | ||
local-offset: -4004, debug-info-variable: '', debug-info-expression: '', | ||
debug-info-location: '' } | ||
callSites: [] | ||
constants: [] | ||
machineFunctionInfo: {} | ||
body: | | ||
bb.0.entry: | ||
renamable $r0 = t2ADDri %stack.0.v, 0, 14, $noreg, $noreg | ||
t2STRi12 killed renamable $r0, %stack.1.s, 0, 14, $noreg :: (store 4 into %ir.s) | ||
renamable $r0 = t2LDRi12 %stack.1.s, 0, 14, $noreg :: (dereferenceable load 4 from %ir.s) | ||
ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp | ||
tBL 14, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp | ||
ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp | ||
tBX_RET 14, $noreg | ||
... |
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