[clang-format] Add Verilog suffixes to the scripts

I decided not to wait for D149088 because it was taking a long time.

The capture group in the regexp was changed to non-capturing.  It
doesn't need to be captured.

Reviewed By: HazardyKnusperkeks, owenpan

Differential Revision: https://reviews.llvm.org/D154467

clang/tools/clang-format/clang-format-diff.py

@@ -61,8 +61,8 @@ def main():
     parser.add_argument(
         "-iregex",
         metavar="PATTERN",
-        default=r".*\.(cpp|cc|c\+\+|cxx|cppm|ccm|cxxm|c\+\+m|c|cl|h|hh|hpp|hxx"
-        r"|m|mm|inc|js|ts|proto|protodevel|java|cs|json)",
+        default=r".*\.(?:cpp|cc|c\+\+|cxx|cppm|ccm|cxxm|c\+\+m|c|cl|h|hh|hpp"
+        r"|hxx|m|mm|inc|js|ts|proto|protodevel|java|cs|json|s?vh?)",
         help="custom pattern selecting file paths to reformat "
         "(case insensitive, overridden by -regex)",
     )

clang/tools/clang-format/git-clang-format

@@ -98,6 +98,7 @@ def main():
       'ts',  # TypeScript
       'cs',  # C Sharp
       'json',  # Json
+      'sv', 'svh', 'v', 'vh', # Verilog
       ])
 
   p = argparse.ArgumentParser(