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Fix MSVC signed/unsigned mismatch warning. NFC.
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RKSimon committed Dec 4, 2023
1 parent 4275da2 commit 83e01ea
Showing 1 changed file with 4 additions and 4 deletions.
8 changes: 4 additions & 4 deletions llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4473,7 +4473,7 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
int Adj = Subtarget.getPreISelOperandLatencyAdjustment();
int Threshold = 1 + Adj;
return !Latency || Latency <= Threshold ? 1 : *Latency - Adj;
return !Latency || Latency <= (unsigned)Threshold ? 1 : *Latency - Adj;
}

const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
Expand All @@ -4490,7 +4490,7 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
if (!Latency)
return std::nullopt;

if (Latency > 1 &&
if (Latency > 1U &&
(Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
Subtarget.isCortexA7())) {
// FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
Expand Down Expand Up @@ -4519,7 +4519,7 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
break;
}
}
} else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
} else if (DefIdx == 0 && Latency > 2U && Subtarget.isSwift()) {
// FIXME: Properly handle all of the latency adjustments for address
// writeback.
switch (DefMCID.getOpcode()) {
Expand Down Expand Up @@ -4836,7 +4836,7 @@ bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
unsigned DefClass = DefMI.getDesc().getSchedClass();
std::optional<unsigned> DefCycle =
ItinData->getOperandCycle(DefClass, DefIdx);
return DefCycle <= 2;
return DefCycle <= 2U;
}
return false;
}
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