Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
[AArch64][v8.5A] Add speculation restriction system registers
This adds some new system registers which can be used to restrict certain types of speculative execution. Patch by Pablo Barrio and David Spickett! Differential revision: https://reviews.llvm.org/D52482 llvm-svn: 343218
- Loading branch information
Showing
9 changed files
with
163 additions
and
5 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,10 @@ | ||
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+specrestrict < %s 2>&1 | FileCheck %s | ||
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s | ||
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-specrestrict < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID | ||
|
||
msr SSBS, #2 | ||
|
||
// CHECK: error: immediate must be an integer in range [0, 1]. | ||
// CHECK-NEXT: msr SSBS, #2 | ||
// NOSPECID: error: expected writable system register or pstate | ||
// NOSPECID-NEXT: msr {{ssbs|SSBS}}, #2 |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,69 @@ | ||
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+specrestrict < %s | FileCheck %s | ||
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s | FileCheck %s | ||
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-specrestrict < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID | ||
|
||
mrs x9, ID_PFR2_EL1 | ||
|
||
// CHECK: mrs x9, {{id_pfr2_el1|ID_PFR2_EL1}} // encoding: [0x89,0x03,0x38,0xd5] | ||
// NOSPECID: error: expected readable system register | ||
// NOSPECID-NEXT: mrs x9, ID_PFR2_EL1 | ||
|
||
mrs x8, SCXTNUM_EL0 | ||
mrs x7, SCXTNUM_EL1 | ||
mrs x6, SCXTNUM_EL2 | ||
mrs x5, SCXTNUM_EL3 | ||
mrs x4, SCXTNUM_EL12 | ||
|
||
// CHECK: mrs x8, {{scxtnum_el0|SCXTNUM_EL0}} // encoding: [0xe8,0xd0,0x3b,0xd5] | ||
// CHECK: mrs x7, {{scxtnum_el1|SCXTNUM_EL1}} // encoding: [0xe7,0xd0,0x38,0xd5] | ||
// CHECK: mrs x6, {{scxtnum_el2|SCXTNUM_EL2}} // encoding: [0xe6,0xd0,0x3c,0xd5] | ||
// CHECK: mrs x5, {{scxtnum_el3|SCXTNUM_EL3}} // encoding: [0xe5,0xd0,0x3e,0xd5] | ||
// CHECK: mrs x4, {{scxtnum_el12|SCXTNUM_EL12}} // encoding: [0xe4,0xd0,0x3d,0xd5] | ||
// NOSPECID: error: expected readable system register | ||
// NOSPECID-NEXT: mrs x8, {{scxtnum_el0|SCXTNUM_EL0}} | ||
// NOSPECID: error: expected readable system register | ||
// NOSPECID-NEXT: mrs x7, {{scxtnum_el1|SCXTNUM_EL1}} | ||
// NOSPECID: error: expected readable system register | ||
// NOSPECID-NEXT: mrs x6, {{scxtnum_el2|SCXTNUM_EL2}} | ||
// NOSPECID: error: expected readable system register | ||
// NOSPECID-NEXT: mrs x5, {{scxtnum_el3|SCXTNUM_EL3}} | ||
// NOSPECID: error: expected readable system register | ||
// NOSPECID-NEXT: mrs x4, {{scxtnum_el12|SCXTNUM_EL12}} | ||
|
||
msr SCXTNUM_EL0, x8 | ||
msr SCXTNUM_EL1, x7 | ||
msr SCXTNUM_EL2, x6 | ||
msr SCXTNUM_EL3, x5 | ||
msr SCXTNUM_EL12, x4 | ||
|
||
// CHECK: msr {{scxtnum_el0|SCXTNUM_EL0}}, x8 // encoding: [0xe8,0xd0,0x1b,0xd5] | ||
// CHECK: msr {{scxtnum_el1|SCXTNUM_EL1}}, x7 // encoding: [0xe7,0xd0,0x18,0xd5] | ||
// CHECK: msr {{scxtnum_el2|SCXTNUM_EL2}}, x6 // encoding: [0xe6,0xd0,0x1c,0xd5] | ||
// CHECK: msr {{scxtnum_el3|SCXTNUM_EL3}}, x5 // encoding: [0xe5,0xd0,0x1e,0xd5] | ||
// CHECK: msr {{scxtnum_el12|SCXTNUM_EL12}}, x4 // encoding: [0xe4,0xd0,0x1d,0xd5] | ||
// NOSPECID: error: expected writable system register | ||
// NOSPECID-NEXT: {{scxtnum_el0|SCXTNUM_EL0}} | ||
// NOSPECID: error: expected writable system register | ||
// NOSPECID-NEXT: {{scxtnum_el1|SCXTNUM_EL1}} | ||
// NOSPECID: error: expected writable system register | ||
// NOSPECID-NEXT: {{scxtnum_el2|SCXTNUM_EL2}} | ||
// NOSPECID: error: expected writable system register | ||
// NOSPECID-NEXT: {{scxtnum_el3|SCXTNUM_EL3}} | ||
// NOSPECID: error: expected writable system register | ||
// NOSPECID-NEXT: {{scxtnum_el12|SCXTNUM_EL12}} | ||
|
||
mrs x2, SSBS | ||
|
||
// CHECK: mrs x2, {{ssbs|SSBS}} // encoding: [0xc2,0x42,0x3b,0xd5] | ||
// NOSPECID: error: expected readable system register | ||
// NOSPECID-NEXT: mrs x2, {{ssbs|SSBS}} | ||
|
||
msr SSBS, x3 | ||
msr SSBS, #1 | ||
|
||
// CHECK: msr {{ssbs|SSBS}}, x3 // encoding: [0xc3,0x42,0x1b,0xd5] | ||
// CHECK: msr {{ssbs|SSBS}}, #1 // encoding: [0x3f,0x41,0x03,0xd5] | ||
// NOSPECID: error: expected writable system register or pstate | ||
// NOSPECID-NEXT: msr {{ssbs|SSBS}}, x3 | ||
// NOSPECID: error: expected writable system register or pstate | ||
// NOSPECID-NEXT: msr {{ssbs|SSBS}}, #1 |
52 changes: 52 additions & 0 deletions
52
llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,52 @@ | ||
# RUN: llvm-mc -triple=aarch64 -mattr=+specrestrict -disassemble < %s | FileCheck %s | ||
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s | ||
# RUN: llvm-mc -triple=aarch64 -mattr=-specrestrict -disassemble < %s | FileCheck %s --check-prefix=NOSPECID | ||
|
||
[0x81 0x03 0x38 0xd5] | ||
|
||
# CHECK: mrs x1, {{id_pfr2_el1|ID_PFR2_EL1}} | ||
# NOSPECID: mrs x1, S3_0_C0_C3_4 | ||
|
||
[0xe8 0xd0 0x3b 0xd5] | ||
[0xe7 0xd0 0x38 0xd5] | ||
[0xe6 0xd0 0x3c 0xd5] | ||
[0xe5 0xd0 0x3e 0xd5] | ||
[0xe4 0xd0 0x3d 0xd5] | ||
|
||
# CHECK: mrs x8, {{scxtnum_el0|SCXTNUM_EL0}} | ||
# CHECK: mrs x7, {{scxtnum_el1|SCXTNUM_EL1}} | ||
# CHECK: mrs x6, {{scxtnum_el2|SCXTNUM_EL2}} | ||
# CHECK: mrs x5, {{scxtnum_el3|SCXTNUM_EL3}} | ||
# CHECK: mrs x4, {{scxtnum_el12|SCXTNUM_EL12}} | ||
# NOSPECID: mrs x8, S3_3_C13_C0_7 | ||
# NOSPECID: mrs x7, S3_0_C13_C0_7 | ||
# NOSPECID: mrs x6, S3_4_C13_C0_7 | ||
# NOSPECID: mrs x5, S3_6_C13_C0_7 | ||
# NOSPECID: mrs x4, S3_5_C13_C0_7 | ||
|
||
[0xe8 0xd0 0x1b 0xd5] | ||
[0xe7 0xd0 0x18 0xd5] | ||
[0xe6 0xd0 0x1c 0xd5] | ||
[0xe5 0xd0 0x1e 0xd5] | ||
[0xe4 0xd0 0x1d 0xd5] | ||
|
||
# CHECK: msr {{scxtnum_el0|SCXTNUM_EL0}}, x8 | ||
# CHECK: msr {{scxtnum_el1|SCXTNUM_EL1}}, x7 | ||
# CHECK: msr {{scxtnum_el2|SCXTNUM_EL2}}, x6 | ||
# CHECK: msr {{scxtnum_el3|SCXTNUM_EL3}}, x5 | ||
# CHECK: msr {{scxtnum_el12|SCXTNUM_EL12}}, x4 | ||
# NOSPECID: msr S3_3_C13_C0_7, x8 | ||
# NOSPECID: msr S3_0_C13_C0_7, x7 | ||
# NOSPECID: msr S3_4_C13_C0_7, x6 | ||
# NOSPECID: msr S3_6_C13_C0_7, x5 | ||
# NOSPECID: msr S3_5_C13_C0_7, x4 | ||
|
||
[0x3f 0x41 0x03 0xd5] | ||
[0xc3 0x42 0x1b 0xd5] | ||
[0xc2 0x42 0x3b 0xd5] | ||
# CHECK: msr SSBS, #1 | ||
# CHECK: msr SSBS, x3 | ||
# CHECK: mrs x2, SSBS | ||
# NOSPECID: msr S0_3_C4_C1_1, xzr | ||
# NOSPECID: msr S3_3_C4_C2_6, x3 | ||
# NOSPECID: mrs x2, S3_3_C4_C2_6 |