Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
[AArch64][SVE2] Asm: add integer multiply-add/subtract (indexed) inst…
…ructions Summary: This patch adds support for the following instructions: MLA mul-add, writing addend (Zda = Zda + Zn * Zm[idx]) MLS mul-sub, writing addend (Zda = Zda + -Zn * Zm[idx]) Predicated forms of these instructions were added in SVE. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: rovka Differential Revision: https://reviews.llvm.org/D61514 llvm-svn: 360682
- Loading branch information
Showing
6 changed files
with
264 additions
and
0 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,64 @@ | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s | ||
|
||
|
||
// ------------------------------------------------------------------------- // | ||
// z register out of range for index | ||
|
||
mla z0.h, z1.h, z8.h[0] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h | ||
// CHECK-NEXT: mla z0.h, z1.h, z8.h[0] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
mla z0.s, z1.s, z8.s[0] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s | ||
// CHECK-NEXT: mla z0.s, z1.s, z8.s[0] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
mla z0.d, z1.d, z16.d[0] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d | ||
// CHECK-NEXT: mla z0.d, z1.d, z16.d[0] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
|
||
// ------------------------------------------------------------------------- // | ||
// Invalid element index | ||
|
||
mla z0.h, z1.h, z2.h[-1] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. | ||
// CHECK-NEXT: mla z0.h, z1.h, z2.h[-1] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
mla z0.h, z1.h, z2.h[8] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. | ||
// CHECK-NEXT: mla z0.h, z1.h, z2.h[8] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
mla z0.s, z1.s, z2.s[-1] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. | ||
// CHECK-NEXT: mla z0.s, z1.s, z2.s[-1] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
mla z0.s, z1.s, z2.s[4] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. | ||
// CHECK-NEXT: mla z0.s, z1.s, z2.s[4] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
mla z0.d, z1.d, z2.d[-1] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. | ||
// CHECK-NEXT: mla z0.d, z1.d, z2.d[-1] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
mla z0.d, z1.d, z2.d[2] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. | ||
// CHECK-NEXT: mla z0.d, z1.d, z2.d[2] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
|
||
// --------------------------------------------------------------------------// | ||
// Negative tests for instructions that are incompatible with movprfx | ||
|
||
movprfx z0.d, p0/z, z7.d | ||
mla z0.d, z1.d, z7.d[1] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx | ||
// CHECK-NEXT: mla z0.d, z1.d, z7.d[1] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,42 @@ | ||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ | ||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ | ||
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ | ||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN | ||
|
||
mla z0.h, z1.h, z7.h[7] | ||
// CHECK-INST: mla z0.h, z1.h, z7.h[7] | ||
// CHECK-ENCODING: [0x20,0x08,0x7f,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: 20 08 7f 44 <unknown> | ||
|
||
mla z0.s, z1.s, z7.s[3] | ||
// CHECK-INST: mla z0.s, z1.s, z7.s[3] | ||
// CHECK-ENCODING: [0x20,0x08,0xbf,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: 20 08 bf 44 <unknown> | ||
|
||
mla z0.d, z1.d, z7.d[1] | ||
// CHECK-INST: mla z0.d, z1.d, z7.d[1] | ||
// CHECK-ENCODING: [0x20,0x08,0xf7,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: 20 08 f7 44 <unknown> | ||
|
||
|
||
// --------------------------------------------------------------------------// | ||
// Test compatibility with MOVPRFX instruction. | ||
|
||
movprfx z0, z7 | ||
// CHECK-INST: movprfx z0, z7 | ||
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: e0 bc 20 04 <unknown> | ||
|
||
mla z0.d, z1.d, z7.d[1] | ||
// CHECK-INST: mla z0.d, z1.d, z7.d[1] | ||
// CHECK-ENCODING: [0x20,0x08,0xf7,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: 20 08 f7 44 <unknown> |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,65 @@ | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s | ||
|
||
|
||
|
||
// ------------------------------------------------------------------------- // | ||
// z register out of range for index | ||
|
||
mls z0.h, z1.h, z8.h[0] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h | ||
// CHECK-NEXT: mls z0.h, z1.h, z8.h[0] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
mls z0.s, z1.s, z8.s[0] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s | ||
// CHECK-NEXT: mls z0.s, z1.s, z8.s[0] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
mls z0.d, z1.d, z16.d[0] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d | ||
// CHECK-NEXT: mls z0.d, z1.d, z16.d[0] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
|
||
// ------------------------------------------------------------------------- // | ||
// Invalid element index | ||
|
||
mls z0.h, z1.h, z2.h[-1] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. | ||
// CHECK-NEXT: mls z0.h, z1.h, z2.h[-1] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
mls z0.h, z1.h, z2.h[8] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. | ||
// CHECK-NEXT: mls z0.h, z1.h, z2.h[8] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
mls z0.s, z1.s, z2.s[-1] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. | ||
// CHECK-NEXT: mls z0.s, z1.s, z2.s[-1] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
mls z0.s, z1.s, z2.s[4] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. | ||
// CHECK-NEXT: mls z0.s, z1.s, z2.s[4] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
mls z0.d, z1.d, z2.d[-1] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. | ||
// CHECK-NEXT: mls z0.d, z1.d, z2.d[-1] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
mls z0.d, z1.d, z2.d[2] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. | ||
// CHECK-NEXT: mls z0.d, z1.d, z2.d[2] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
||
|
||
// --------------------------------------------------------------------------// | ||
// Negative tests for instructions that are incompatible with movprfx | ||
|
||
movprfx z0.d, p0/z, z7.d | ||
mls z0.d, z1.d, z7.d[1] | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx | ||
// CHECK-NEXT: mls z0.d, z1.d, z7.d[1] | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,42 @@ | ||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ | ||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ | ||
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ | ||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN | ||
|
||
mls z0.h, z1.h, z7.h[7] | ||
// CHECK-INST: mls z0.h, z1.h, z7.h[7] | ||
// CHECK-ENCODING: [0x20,0x0c,0x7f,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: 20 0c 7f 44 <unknown> | ||
|
||
mls z0.s, z1.s, z7.s[3] | ||
// CHECK-INST: mls z0.s, z1.s, z7.s[3] | ||
// CHECK-ENCODING: [0x20,0x0c,0xbf,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: 20 0c bf 44 <unknown> | ||
|
||
mls z0.d, z1.d, z7.d[1] | ||
// CHECK-INST: mls z0.d, z1.d, z7.d[1] | ||
// CHECK-ENCODING: [0x20,0x0c,0xf7,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: 20 0c f7 44 <unknown> | ||
|
||
|
||
// --------------------------------------------------------------------------// | ||
// Test compatibility with MOVPRFX instruction. | ||
|
||
movprfx z0, z7 | ||
// CHECK-INST: movprfx z0, z7 | ||
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: e0 bc 20 04 <unknown> | ||
|
||
mls z0.d, z1.d, z7.d[1] | ||
// CHECK-INST: mls z0.d, z1.d, z7.d[1] | ||
// CHECK-ENCODING: [0x20,0x0c,0xf7,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: 20 0c f7 44 <unknown> |