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[ARM] Regenerate test checks (NFC)
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@nikic
nikic committed Dec 21, 2022
1 parent 50ddc8c commit 87679b1
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507 changes: 459 additions & 48 deletions llvm/test/CodeGen/ARM/ParallelDSP/aliasing.ll
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198 changes: 165 additions & 33 deletions llvm/test/CodeGen/ARM/ParallelDSP/blocks.ll
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@@ -1,12 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -arm-parallel-dsp -dce -mtriple=armv7-a -S %s -o - | FileCheck %s

; CHECK-LABEL: single_block
; CHECK: [[CAST_A:%[^ ]+]] = bitcast i16* %a to i32*
; CHECK: [[A:%[^ ]+]] = load i32, i32* [[CAST_A]]
; CHECK: [[CAST_B:%[^ ]+]] = bitcast i16* %b to i32*
; CHECK: [[B:%[^ ]+]] = load i32, i32* [[CAST_B]]
; CHECK: call i32 @llvm.arm.smlad(i32 [[A]], i32 [[B]], i32 %acc)
define i32 @single_block(i16* %a, i16* %b, i32 %acc) {
; CHECK-LABEL: @single_block(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast i16* [[A:%.*]] to i32*
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 2
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i16* [[B:%.*]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 2
; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP1]], i32 [[TMP3]], i32 [[ACC:%.*]])
; CHECK-NEXT: ret i32 [[TMP4]]
;
entry:
%ld.a.0 = load i16, i16* %a
%sext.a.0 = sext i16 %ld.a.0 to i32
Expand All @@ -25,13 +29,16 @@ entry:
ret i32 %res
}

; CHECK-LABEL: single_block_64
; CHECK: [[CAST_A:%[^ ]+]] = bitcast i16* %a to i32*
; CHECK: [[A:%[^ ]+]] = load i32, i32* [[CAST_A]]
; CHECK: [[CAST_B:%[^ ]+]] = bitcast i16* %b to i32*
; CHECK: [[B:%[^ ]+]] = load i32, i32* [[CAST_B]]
; CHECK: call i64 @llvm.arm.smlald(i32 [[A]], i32 [[B]], i64 %acc)
define i64 @single_block_64(i16* %a, i16* %b, i64 %acc) {
; CHECK-LABEL: @single_block_64(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast i16* [[A:%.*]] to i32*
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 2
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i16* [[B:%.*]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 2
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.arm.smlald(i32 [[TMP1]], i32 [[TMP3]], i64 [[ACC:%.*]])
; CHECK-NEXT: ret i64 [[TMP4]]
;
entry:
%ld.a.0 = load i16, i16* %a
%sext.a.0 = sext i16 %ld.a.0 to i32
Expand All @@ -52,13 +59,19 @@ entry:
ret i64 %res
}

; CHECK-LABEL: multi_block
; CHECK: [[CAST_A:%[^ ]+]] = bitcast i16* %a to i32*
; CHECK: [[A:%[^ ]+]] = load i32, i32* [[CAST_A]]
; CHECK: [[CAST_B:%[^ ]+]] = bitcast i16* %b to i32*
; CHECK: [[B:%[^ ]+]] = load i32, i32* [[CAST_B]]
; CHECK: call i32 @llvm.arm.smlad(i32 [[A]], i32 [[B]], i32 0)
define i32 @multi_block(i16* %a, i16* %b, i32 %acc) {
; CHECK-LABEL: @multi_block(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast i16* [[A:%.*]] to i32*
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 2
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i16* [[B:%.*]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 2
; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP1]], i32 [[TMP3]], i32 0)
; CHECK-NEXT: br label [[BB_1:%.*]]
; CHECK: bb.1:
; CHECK-NEXT: [[RES:%.*]] = add i32 [[TMP4]], [[ACC:%.*]]
; CHECK-NEXT: ret i32 [[RES]]
;
entry:
%ld.a.0 = load i16, i16* %a
%sext.a.0 = sext i16 %ld.a.0 to i32
Expand All @@ -80,13 +93,19 @@ bb.1:
ret i32 %res
}

; CHECK-LABEL: multi_block_64
; CHECK: [[CAST_A:%[^ ]+]] = bitcast i16* %a to i32*
; CHECK: [[A:%[^ ]+]] = load i32, i32* [[CAST_A]]
; CHECK: [[CAST_B:%[^ ]+]] = bitcast i16* %b to i32*
; CHECK: [[B:%[^ ]+]] = load i32, i32* [[CAST_B]]
; CHECK: call i64 @llvm.arm.smlald(i32 [[A]], i32 [[B]], i64 0)
define i64 @multi_block_64(i16* %a, i16* %b, i64 %acc) {
; CHECK-LABEL: @multi_block_64(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast i16* [[A:%.*]] to i32*
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 2
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i16* [[B:%.*]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 2
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.arm.smlald(i32 [[TMP1]], i32 [[TMP3]], i64 0)
; CHECK-NEXT: br label [[BB_1:%.*]]
; CHECK: bb.1:
; CHECK-NEXT: [[RES:%.*]] = add i64 [[TMP4]], [[ACC:%.*]]
; CHECK-NEXT: ret i64 [[RES]]
;
entry:
%ld.a.0 = load i16, i16* %a
%sext.a.0 = sext i16 %ld.a.0 to i32
Expand All @@ -110,9 +129,27 @@ bb.1:
ret i64 %res
}

; CHECK-LABEL: multi_block_1
; CHECK-NOT: call i32 @llvm.arm.smlad
define i32 @multi_block_1(i16* %a, i16* %b, i32 %acc) {
; CHECK-LABEL: @multi_block_1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, i16* [[A:%.*]], align 2
; CHECK-NEXT: [[SEXT_A_0:%.*]] = sext i16 [[LD_A_0]] to i32
; CHECK-NEXT: [[LD_B_0:%.*]] = load i16, i16* [[B:%.*]], align 2
; CHECK-NEXT: [[SEXT_B_0:%.*]] = sext i16 [[LD_B_0]] to i32
; CHECK-NEXT: [[MUL_0:%.*]] = mul i32 [[SEXT_A_0]], [[SEXT_B_0]]
; CHECK-NEXT: br label [[BB_1:%.*]]
; CHECK: bb.1:
; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, i16* [[A]], i32 1
; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, i16* [[B]], i32 1
; CHECK-NEXT: [[LD_A_1:%.*]] = load i16, i16* [[ADDR_A_1]], align 2
; CHECK-NEXT: [[SEXT_A_1:%.*]] = sext i16 [[LD_A_1]] to i32
; CHECK-NEXT: [[LD_B_1:%.*]] = load i16, i16* [[ADDR_B_1]], align 2
; CHECK-NEXT: [[SEXT_B_1:%.*]] = sext i16 [[LD_B_1]] to i32
; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[SEXT_A_1]], [[SEXT_B_1]]
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[MUL_0]], [[MUL_1]]
; CHECK-NEXT: [[RES:%.*]] = add i32 [[ADD]], [[ACC:%.*]]
; CHECK-NEXT: ret i32 [[RES]]
;
entry:
%ld.a.0 = load i16, i16* %a
%sext.a.0 = sext i16 %ld.a.0 to i32
Expand All @@ -136,12 +173,44 @@ bb.1:

; TODO: Four smlads should be generated here, but mul.0 and mul.3 remain as
; scalars.
; CHECK-LABEL: num_load_limit
; CHECK: call i32 @llvm.arm.smlad
; CHECK: call i32 @llvm.arm.smlad
; CHECK: call i32 @llvm.arm.smlad
; CHECK-NOT: call i32 @llvm.arm.smlad
define i32 @num_load_limit(i16* %a, i16* %b, i32 %acc) {
; CHECK-LABEL: @num_load_limit(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast i16* [[A:%.*]] to i32*
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 2
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 16
; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
; CHECK-NEXT: [[TMP6:%.*]] = sext i16 [[TMP5]] to i32
; CHECK-NEXT: [[TMP7:%.*]] = bitcast i16* [[B:%.*]] to i32*
; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 2
; CHECK-NEXT: [[TMP9:%.*]] = trunc i32 [[TMP8]] to i16
; CHECK-NEXT: [[TMP10:%.*]] = sext i16 [[TMP9]] to i32
; CHECK-NEXT: [[MUL_0:%.*]] = mul i32 [[TMP3]], [[TMP10]]
; CHECK-NEXT: [[ADDR_B_3:%.*]] = getelementptr i16, i16* [[B]], i32 3
; CHECK-NEXT: [[LD_B_3:%.*]] = load i16, i16* [[ADDR_B_3]], align 2
; CHECK-NEXT: [[SEXT_B_3:%.*]] = sext i16 [[LD_B_3]] to i32
; CHECK-NEXT: [[MUL_3:%.*]] = mul i32 [[TMP6]], [[SEXT_B_3]]
; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[MUL_3]], [[ACC:%.*]]
; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[MUL_0]], [[TMP11]]
; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP1]], i32 [[TMP8]], i32 [[TMP12]])
; CHECK-NEXT: [[ADDR_A_4:%.*]] = getelementptr i16, i16* [[A]], i32 4
; CHECK-NEXT: [[ADDR_B_4:%.*]] = getelementptr i16, i16* [[B]], i32 4
; CHECK-NEXT: [[TMP14:%.*]] = bitcast i16* [[ADDR_A_4]] to i32*
; CHECK-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 2
; CHECK-NEXT: [[TMP16:%.*]] = bitcast i16* [[ADDR_B_4]] to i32*
; CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 2
; CHECK-NEXT: [[TMP18:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP15]], i32 [[TMP17]], i32 [[TMP13]])
; CHECK-NEXT: [[ADDR_A_6:%.*]] = getelementptr i16, i16* [[A]], i32 6
; CHECK-NEXT: [[ADDR_B_6:%.*]] = getelementptr i16, i16* [[B]], i32 6
; CHECK-NEXT: [[TMP19:%.*]] = bitcast i16* [[ADDR_A_6]] to i32*
; CHECK-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 2
; CHECK-NEXT: [[TMP21:%.*]] = bitcast i16* [[ADDR_B_6]] to i32*
; CHECK-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 2
; CHECK-NEXT: [[TMP23:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP20]], i32 [[TMP22]], i32 [[TMP18]])
; CHECK-NEXT: ret i32 [[TMP23]]
;
entry:
%ld.a.0 = load i16, i16* %a
%sext.a.0 = sext i16 %ld.a.0 to i32
Expand Down Expand Up @@ -212,9 +281,72 @@ entry:
ret i32 %res
}

; CHECK-LABEL: too_many_loads
; CHECK-NOT: call i32 @llvm.arm.smlad
define i32 @too_many_loads(i16* %a, i16* %b, i32 %acc) {
; CHECK-LABEL: @too_many_loads(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, i16* [[A:%.*]], align 2
; CHECK-NEXT: [[SEXT_A_0:%.*]] = sext i16 [[LD_A_0]] to i32
; CHECK-NEXT: [[LD_B_0:%.*]] = load i16, i16* [[B:%.*]], align 2
; CHECK-NEXT: [[SEXT_B_0:%.*]] = sext i16 [[LD_B_0]] to i32
; CHECK-NEXT: [[MUL_0:%.*]] = mul i32 [[SEXT_A_0]], [[SEXT_B_0]]
; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, i16* [[A]], i32 1
; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, i16* [[B]], i32 1
; CHECK-NEXT: [[LD_A_1:%.*]] = load i16, i16* [[ADDR_A_1]], align 2
; CHECK-NEXT: [[SEXT_A_1:%.*]] = sext i16 [[LD_A_1]] to i32
; CHECK-NEXT: [[LD_B_1:%.*]] = load i16, i16* [[ADDR_B_1]], align 2
; CHECK-NEXT: [[SEXT_B_1:%.*]] = sext i16 [[LD_B_1]] to i32
; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[SEXT_A_1]], [[SEXT_B_1]]
; CHECK-NEXT: [[ADD_0:%.*]] = add i32 [[MUL_0]], [[MUL_1]]
; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[SEXT_A_0]], [[SEXT_B_0]]
; CHECK-NEXT: [[ADDR_B_3:%.*]] = getelementptr i16, i16* [[B]], i32 3
; CHECK-NEXT: [[LD_B_3:%.*]] = load i16, i16* [[ADDR_B_3]], align 2
; CHECK-NEXT: [[SEXT_B_3:%.*]] = sext i16 [[LD_B_3]] to i32
; CHECK-NEXT: [[MUL_3:%.*]] = mul i32 [[SEXT_A_1]], [[SEXT_B_3]]
; CHECK-NEXT: [[ADD_3:%.*]] = add i32 [[MUL_2]], [[MUL_3]]
; CHECK-NEXT: [[ADDR_A_4:%.*]] = getelementptr i16, i16* [[A]], i32 4
; CHECK-NEXT: [[ADDR_B_4:%.*]] = getelementptr i16, i16* [[B]], i32 4
; CHECK-NEXT: [[LD_A_4:%.*]] = load i16, i16* [[ADDR_A_4]], align 2
; CHECK-NEXT: [[SEXT_A_4:%.*]] = sext i16 [[LD_A_4]] to i32
; CHECK-NEXT: [[LD_B_4:%.*]] = load i16, i16* [[ADDR_B_4]], align 2
; CHECK-NEXT: [[SEXT_B_4:%.*]] = sext i16 [[LD_B_4]] to i32
; CHECK-NEXT: [[MUL_4:%.*]] = mul i32 [[SEXT_A_4]], [[SEXT_B_4]]
; CHECK-NEXT: [[ADDR_A_5:%.*]] = getelementptr i16, i16* [[A]], i32 5
; CHECK-NEXT: [[ADDR_B_5:%.*]] = getelementptr i16, i16* [[B]], i32 5
; CHECK-NEXT: [[LD_A_5:%.*]] = load i16, i16* [[ADDR_A_5]], align 2
; CHECK-NEXT: [[SEXT_A_5:%.*]] = sext i16 [[LD_A_5]] to i32
; CHECK-NEXT: [[LD_B_5:%.*]] = load i16, i16* [[ADDR_B_5]], align 2
; CHECK-NEXT: [[SEXT_B_5:%.*]] = sext i16 [[LD_B_5]] to i32
; CHECK-NEXT: [[MUL_5:%.*]] = mul i32 [[SEXT_A_5]], [[SEXT_B_5]]
; CHECK-NEXT: [[ADD_5:%.*]] = add i32 [[MUL_4]], [[MUL_5]]
; CHECK-NEXT: [[ADDR_A_6:%.*]] = getelementptr i16, i16* [[A]], i32 6
; CHECK-NEXT: [[ADDR_B_6:%.*]] = getelementptr i16, i16* [[B]], i32 6
; CHECK-NEXT: [[LD_A_6:%.*]] = load i16, i16* [[ADDR_A_6]], align 2
; CHECK-NEXT: [[SEXT_A_6:%.*]] = sext i16 [[LD_A_6]] to i32
; CHECK-NEXT: [[LD_B_6:%.*]] = load i16, i16* [[ADDR_B_6]], align 2
; CHECK-NEXT: [[SEXT_B_6:%.*]] = sext i16 [[LD_B_6]] to i32
; CHECK-NEXT: [[MUL_6:%.*]] = mul i32 [[SEXT_A_6]], [[SEXT_B_6]]
; CHECK-NEXT: [[ADDR_A_7:%.*]] = getelementptr i16, i16* [[A]], i32 7
; CHECK-NEXT: [[ADDR_B_7:%.*]] = getelementptr i16, i16* [[B]], i32 7
; CHECK-NEXT: [[LD_A_7:%.*]] = load i16, i16* [[ADDR_A_7]], align 2
; CHECK-NEXT: [[SEXT_A_7:%.*]] = sext i16 [[LD_A_7]] to i32
; CHECK-NEXT: [[LD_B_7:%.*]] = load i16, i16* [[ADDR_B_7]], align 2
; CHECK-NEXT: [[SEXT_B_7:%.*]] = sext i16 [[LD_B_7]] to i32
; CHECK-NEXT: [[MUL_7:%.*]] = mul i32 [[SEXT_A_7]], [[SEXT_B_7]]
; CHECK-NEXT: [[ADD_7:%.*]] = add i32 [[MUL_6]], [[MUL_7]]
; CHECK-NEXT: [[ADDR_A_8:%.*]] = getelementptr i16, i16* [[A]], i32 7
; CHECK-NEXT: [[ADDR_B_8:%.*]] = getelementptr i16, i16* [[B]], i32 7
; CHECK-NEXT: [[LD_A_8:%.*]] = load i16, i16* [[ADDR_A_8]], align 2
; CHECK-NEXT: [[SEXT_A_8:%.*]] = sext i16 [[LD_A_8]] to i32
; CHECK-NEXT: [[LD_B_8:%.*]] = load i16, i16* [[ADDR_B_8]], align 2
; CHECK-NEXT: [[SEXT_B_8:%.*]] = sext i16 [[LD_B_8]] to i32
; CHECK-NEXT: [[MUL_8:%.*]] = mul i32 [[SEXT_A_8]], [[SEXT_B_8]]
; CHECK-NEXT: [[ADD_10:%.*]] = add i32 [[ADD_7]], [[ADD_5]]
; CHECK-NEXT: [[ADD_11:%.*]] = add i32 [[ADD_3]], [[ADD_0]]
; CHECK-NEXT: [[ADD_12:%.*]] = add i32 [[ADD_10]], [[ADD_11]]
; CHECK-NEXT: [[ADD_13:%.*]] = add i32 [[ADD_12]], [[ACC:%.*]]
; CHECK-NEXT: [[RES:%.*]] = add i32 [[ADD_13]], [[MUL_8]]
; CHECK-NEXT: ret i32 [[RES]]
;
entry:
%ld.a.0 = load i16, i16* %a
%sext.a.0 = sext i16 %ld.a.0 to i32
Expand Down

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