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[PPC64] Added vector registers.
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The Registers_ppc64 class needed a couple of changes, both to accommodate the
new registers as well as to handle the overlaps of VS register set
without wasting space.

The save/restore code of V and VS registers was added.
As VS registers depend on the VMX extension, they are processed only if
VMX support is detected (_ARCH_PWR8 for now).

Patch by Leandro Lupori!

Differential Revision: https://reviews.llvm.org/D41906

llvm-svn: 322596
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@mstorsjo
mstorsjo committed Jan 16, 2018
1 parent af4ddd5 commit 89e636c
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10 changes: 5 additions & 5 deletions libunwind/include/__libunwind_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86 8
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86_64 32
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC 112
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC64 110
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC64 116
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM64 95
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM 287
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K 31
Expand All @@ -42,8 +42,8 @@
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86_64
# elif defined(__powerpc64__)
# define _LIBUNWIND_TARGET_PPC64 1
# define _LIBUNWIND_CONTEXT_SIZE 136
# define _LIBUNWIND_CURSOR_SIZE 148
# define _LIBUNWIND_CONTEXT_SIZE 167
# define _LIBUNWIND_CURSOR_SIZE 179
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC64
# elif defined(__ppc__)
# define _LIBUNWIND_TARGET_PPC 1
Expand Down Expand Up @@ -96,8 +96,8 @@
# define _LIBUNWIND_TARGET_OR1K 1
# define _LIBUNWIND_TARGET_MIPS_O32 1
# define _LIBUNWIND_TARGET_MIPS_NEWABI 1
# define _LIBUNWIND_CONTEXT_SIZE 136
# define _LIBUNWIND_CURSOR_SIZE 148
# define _LIBUNWIND_CONTEXT_SIZE 167
# define _LIBUNWIND_CURSOR_SIZE 179
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER 287
#endif // _LIBUNWIND_IS_NATIVE_ONLY

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290 changes: 180 additions & 110 deletions libunwind/include/libunwind.h
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Original file line number Diff line number Diff line change
Expand Up @@ -327,116 +327,186 @@ enum {

// 64-bit ppc register numbers
enum {
UNW_PPC64_R0 = 0,
UNW_PPC64_R1 = 1,
UNW_PPC64_R2 = 2,
UNW_PPC64_R3 = 3,
UNW_PPC64_R4 = 4,
UNW_PPC64_R5 = 5,
UNW_PPC64_R6 = 6,
UNW_PPC64_R7 = 7,
UNW_PPC64_R8 = 8,
UNW_PPC64_R9 = 9,
UNW_PPC64_R10 = 10,
UNW_PPC64_R11 = 11,
UNW_PPC64_R12 = 12,
UNW_PPC64_R13 = 13,
UNW_PPC64_R14 = 14,
UNW_PPC64_R15 = 15,
UNW_PPC64_R16 = 16,
UNW_PPC64_R17 = 17,
UNW_PPC64_R18 = 18,
UNW_PPC64_R19 = 19,
UNW_PPC64_R20 = 20,
UNW_PPC64_R21 = 21,
UNW_PPC64_R22 = 22,
UNW_PPC64_R23 = 23,
UNW_PPC64_R24 = 24,
UNW_PPC64_R25 = 25,
UNW_PPC64_R26 = 26,
UNW_PPC64_R27 = 27,
UNW_PPC64_R28 = 28,
UNW_PPC64_R29 = 29,
UNW_PPC64_R30 = 30,
UNW_PPC64_R31 = 31,
UNW_PPC64_F0 = 32,
UNW_PPC64_F1 = 33,
UNW_PPC64_F2 = 34,
UNW_PPC64_F3 = 35,
UNW_PPC64_F4 = 36,
UNW_PPC64_F5 = 37,
UNW_PPC64_F6 = 38,
UNW_PPC64_F7 = 39,
UNW_PPC64_F8 = 40,
UNW_PPC64_F9 = 41,
UNW_PPC64_F10 = 42,
UNW_PPC64_F11 = 43,
UNW_PPC64_F12 = 44,
UNW_PPC64_F13 = 45,
UNW_PPC64_F14 = 46,
UNW_PPC64_F15 = 47,
UNW_PPC64_F16 = 48,
UNW_PPC64_F17 = 49,
UNW_PPC64_F18 = 50,
UNW_PPC64_F19 = 51,
UNW_PPC64_F20 = 52,
UNW_PPC64_F21 = 53,
UNW_PPC64_F22 = 54,
UNW_PPC64_F23 = 55,
UNW_PPC64_F24 = 56,
UNW_PPC64_F25 = 57,
UNW_PPC64_F26 = 58,
UNW_PPC64_F27 = 59,
UNW_PPC64_F28 = 60,
UNW_PPC64_F29 = 61,
UNW_PPC64_F30 = 62,
UNW_PPC64_F31 = 63,
UNW_PPC64_LR = 64,
UNW_PPC64_CTR = 65,
UNW_PPC64_CR0 = 66,
UNW_PPC64_CR1 = 67,
UNW_PPC64_CR2 = 68,
UNW_PPC64_CR3 = 69,
UNW_PPC64_CR4 = 70,
UNW_PPC64_CR5 = 71,
UNW_PPC64_CR6 = 72,
UNW_PPC64_CR7 = 73,
UNW_PPC64_XER = 74,
UNW_PPC64_V0 = 75,
UNW_PPC64_V1 = 76,
UNW_PPC64_V2 = 77,
UNW_PPC64_V3 = 78,
UNW_PPC64_V4 = 79,
UNW_PPC64_V5 = 80,
UNW_PPC64_V6 = 81,
UNW_PPC64_V7 = 82,
UNW_PPC64_V8 = 83,
UNW_PPC64_V9 = 84,
UNW_PPC64_V10 = 85,
UNW_PPC64_V11 = 86,
UNW_PPC64_V12 = 87,
UNW_PPC64_V13 = 88,
UNW_PPC64_V14 = 89,
UNW_PPC64_V15 = 90,
UNW_PPC64_V16 = 91,
UNW_PPC64_V17 = 92,
UNW_PPC64_V18 = 93,
UNW_PPC64_V19 = 94,
UNW_PPC64_V20 = 95,
UNW_PPC64_V21 = 96,
UNW_PPC64_V22 = 97,
UNW_PPC64_V23 = 98,
UNW_PPC64_V24 = 99,
UNW_PPC64_V25 = 100,
UNW_PPC64_V26 = 101,
UNW_PPC64_V27 = 102,
UNW_PPC64_V28 = 103,
UNW_PPC64_V29 = 104,
UNW_PPC64_V30 = 105,
UNW_PPC64_V31 = 106,
UNW_PPC64_VRSAVE = 107,
UNW_PPC64_VSCR = 108,
UNW_PPC64_FPSCR = 109
UNW_PPC64_R0 = 0,
UNW_PPC64_R1 = 1,
UNW_PPC64_R2 = 2,
UNW_PPC64_R3 = 3,
UNW_PPC64_R4 = 4,
UNW_PPC64_R5 = 5,
UNW_PPC64_R6 = 6,
UNW_PPC64_R7 = 7,
UNW_PPC64_R8 = 8,
UNW_PPC64_R9 = 9,
UNW_PPC64_R10 = 10,
UNW_PPC64_R11 = 11,
UNW_PPC64_R12 = 12,
UNW_PPC64_R13 = 13,
UNW_PPC64_R14 = 14,
UNW_PPC64_R15 = 15,
UNW_PPC64_R16 = 16,
UNW_PPC64_R17 = 17,
UNW_PPC64_R18 = 18,
UNW_PPC64_R19 = 19,
UNW_PPC64_R20 = 20,
UNW_PPC64_R21 = 21,
UNW_PPC64_R22 = 22,
UNW_PPC64_R23 = 23,
UNW_PPC64_R24 = 24,
UNW_PPC64_R25 = 25,
UNW_PPC64_R26 = 26,
UNW_PPC64_R27 = 27,
UNW_PPC64_R28 = 28,
UNW_PPC64_R29 = 29,
UNW_PPC64_R30 = 30,
UNW_PPC64_R31 = 31,
UNW_PPC64_F0 = 32,
UNW_PPC64_F1 = 33,
UNW_PPC64_F2 = 34,
UNW_PPC64_F3 = 35,
UNW_PPC64_F4 = 36,
UNW_PPC64_F5 = 37,
UNW_PPC64_F6 = 38,
UNW_PPC64_F7 = 39,
UNW_PPC64_F8 = 40,
UNW_PPC64_F9 = 41,
UNW_PPC64_F10 = 42,
UNW_PPC64_F11 = 43,
UNW_PPC64_F12 = 44,
UNW_PPC64_F13 = 45,
UNW_PPC64_F14 = 46,
UNW_PPC64_F15 = 47,
UNW_PPC64_F16 = 48,
UNW_PPC64_F17 = 49,
UNW_PPC64_F18 = 50,
UNW_PPC64_F19 = 51,
UNW_PPC64_F20 = 52,
UNW_PPC64_F21 = 53,
UNW_PPC64_F22 = 54,
UNW_PPC64_F23 = 55,
UNW_PPC64_F24 = 56,
UNW_PPC64_F25 = 57,
UNW_PPC64_F26 = 58,
UNW_PPC64_F27 = 59,
UNW_PPC64_F28 = 60,
UNW_PPC64_F29 = 61,
UNW_PPC64_F30 = 62,
UNW_PPC64_F31 = 63,
// 64: reserved
UNW_PPC64_LR = 65,
UNW_PPC64_CTR = 66,
// 67: reserved
UNW_PPC64_CR0 = 68,
UNW_PPC64_CR1 = 69,
UNW_PPC64_CR2 = 70,
UNW_PPC64_CR3 = 71,
UNW_PPC64_CR4 = 72,
UNW_PPC64_CR5 = 73,
UNW_PPC64_CR6 = 74,
UNW_PPC64_CR7 = 75,
UNW_PPC64_XER = 76,
UNW_PPC64_V0 = 77,
UNW_PPC64_V1 = 78,
UNW_PPC64_V2 = 79,
UNW_PPC64_V3 = 80,
UNW_PPC64_V4 = 81,
UNW_PPC64_V5 = 82,
UNW_PPC64_V6 = 83,
UNW_PPC64_V7 = 84,
UNW_PPC64_V8 = 85,
UNW_PPC64_V9 = 86,
UNW_PPC64_V10 = 87,
UNW_PPC64_V11 = 88,
UNW_PPC64_V12 = 89,
UNW_PPC64_V13 = 90,
UNW_PPC64_V14 = 91,
UNW_PPC64_V15 = 92,
UNW_PPC64_V16 = 93,
UNW_PPC64_V17 = 94,
UNW_PPC64_V18 = 95,
UNW_PPC64_V19 = 96,
UNW_PPC64_V20 = 97,
UNW_PPC64_V21 = 98,
UNW_PPC64_V22 = 99,
UNW_PPC64_V23 = 100,
UNW_PPC64_V24 = 101,
UNW_PPC64_V25 = 102,
UNW_PPC64_V26 = 103,
UNW_PPC64_V27 = 104,
UNW_PPC64_V28 = 105,
UNW_PPC64_V29 = 106,
UNW_PPC64_V30 = 107,
UNW_PPC64_V31 = 108,
// 109, 111-113: OpenPOWER ELF V2 ABI: reserved
// Borrowing VRSAVE number from PPC32.
UNW_PPC64_VRSAVE = 109,
UNW_PPC64_VSCR = 110,
UNW_PPC64_TFHAR = 114,
UNW_PPC64_TFIAR = 115,
UNW_PPC64_TEXASR = 116,
UNW_PPC64_VS0 = UNW_PPC64_F0,
UNW_PPC64_VS1 = UNW_PPC64_F1,
UNW_PPC64_VS2 = UNW_PPC64_F2,
UNW_PPC64_VS3 = UNW_PPC64_F3,
UNW_PPC64_VS4 = UNW_PPC64_F4,
UNW_PPC64_VS5 = UNW_PPC64_F5,
UNW_PPC64_VS6 = UNW_PPC64_F6,
UNW_PPC64_VS7 = UNW_PPC64_F7,
UNW_PPC64_VS8 = UNW_PPC64_F8,
UNW_PPC64_VS9 = UNW_PPC64_F9,
UNW_PPC64_VS10 = UNW_PPC64_F10,
UNW_PPC64_VS11 = UNW_PPC64_F11,
UNW_PPC64_VS12 = UNW_PPC64_F12,
UNW_PPC64_VS13 = UNW_PPC64_F13,
UNW_PPC64_VS14 = UNW_PPC64_F14,
UNW_PPC64_VS15 = UNW_PPC64_F15,
UNW_PPC64_VS16 = UNW_PPC64_F16,
UNW_PPC64_VS17 = UNW_PPC64_F17,
UNW_PPC64_VS18 = UNW_PPC64_F18,
UNW_PPC64_VS19 = UNW_PPC64_F19,
UNW_PPC64_VS20 = UNW_PPC64_F20,
UNW_PPC64_VS21 = UNW_PPC64_F21,
UNW_PPC64_VS22 = UNW_PPC64_F22,
UNW_PPC64_VS23 = UNW_PPC64_F23,
UNW_PPC64_VS24 = UNW_PPC64_F24,
UNW_PPC64_VS25 = UNW_PPC64_F25,
UNW_PPC64_VS26 = UNW_PPC64_F26,
UNW_PPC64_VS27 = UNW_PPC64_F27,
UNW_PPC64_VS28 = UNW_PPC64_F28,
UNW_PPC64_VS29 = UNW_PPC64_F29,
UNW_PPC64_VS30 = UNW_PPC64_F30,
UNW_PPC64_VS31 = UNW_PPC64_F31,
UNW_PPC64_VS32 = UNW_PPC64_V0,
UNW_PPC64_VS33 = UNW_PPC64_V1,
UNW_PPC64_VS34 = UNW_PPC64_V2,
UNW_PPC64_VS35 = UNW_PPC64_V3,
UNW_PPC64_VS36 = UNW_PPC64_V4,
UNW_PPC64_VS37 = UNW_PPC64_V5,
UNW_PPC64_VS38 = UNW_PPC64_V6,
UNW_PPC64_VS39 = UNW_PPC64_V7,
UNW_PPC64_VS40 = UNW_PPC64_V8,
UNW_PPC64_VS41 = UNW_PPC64_V9,
UNW_PPC64_VS42 = UNW_PPC64_V10,
UNW_PPC64_VS43 = UNW_PPC64_V11,
UNW_PPC64_VS44 = UNW_PPC64_V12,
UNW_PPC64_VS45 = UNW_PPC64_V13,
UNW_PPC64_VS46 = UNW_PPC64_V14,
UNW_PPC64_VS47 = UNW_PPC64_V15,
UNW_PPC64_VS48 = UNW_PPC64_V16,
UNW_PPC64_VS49 = UNW_PPC64_V17,
UNW_PPC64_VS50 = UNW_PPC64_V18,
UNW_PPC64_VS51 = UNW_PPC64_V19,
UNW_PPC64_VS52 = UNW_PPC64_V20,
UNW_PPC64_VS53 = UNW_PPC64_V21,
UNW_PPC64_VS54 = UNW_PPC64_V22,
UNW_PPC64_VS55 = UNW_PPC64_V23,
UNW_PPC64_VS56 = UNW_PPC64_V24,
UNW_PPC64_VS57 = UNW_PPC64_V25,
UNW_PPC64_VS58 = UNW_PPC64_V26,
UNW_PPC64_VS59 = UNW_PPC64_V27,
UNW_PPC64_VS60 = UNW_PPC64_V28,
UNW_PPC64_VS61 = UNW_PPC64_V29,
UNW_PPC64_VS62 = UNW_PPC64_V30,
UNW_PPC64_VS63 = UNW_PPC64_V31
};

// 64-bit ARM64 registers
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