Skip to content

Commit

Permalink
[RISCV] Correct copyPhysReg for GPRPF64. (#70419)
Browse files Browse the repository at this point in the history 
GPRF64 represents a pair of registers. We were only copying the even
part. We need to copy the odd part too.
  • Loading branch information
@topperc @tru
topperc authored and tru committed Oct 30, 2023
1 parent 615beae commit 8c8abe6
Show file tree
Hide file tree
Showing 3 changed files with 34 additions and 5 deletions.
19 changes: 14 additions & 5 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -299,18 +299,27 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MCRegister SrcReg, bool KillSrc) const {
const TargetRegisterInfo *TRI = STI.getRegisterInfo();

if (RISCV::GPRPF64RegClass.contains(DstReg))
DstReg = TRI->getSubReg(DstReg, RISCV::sub_32);
if (RISCV::GPRPF64RegClass.contains(SrcReg))
SrcReg = TRI->getSubReg(SrcReg, RISCV::sub_32);

if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
.addReg(SrcReg, getKillRegState(KillSrc))
.addImm(0);
return;
}

if (RISCV::GPRPF64RegClass.contains(DstReg, SrcReg)) {
// Emit an ADDI for both parts of GPRPF64.
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI),
TRI->getSubReg(DstReg, RISCV::sub_32))
.addReg(TRI->getSubReg(SrcReg, RISCV::sub_32), getKillRegState(KillSrc))
.addImm(0);
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI),
TRI->getSubReg(DstReg, RISCV::sub_32_hi))
.addReg(TRI->getSubReg(SrcReg, RISCV::sub_32_hi),
getKillRegState(KillSrc))
.addImm(0);
return;
}

// Handle copy from csr
if (RISCV::VCSRRegClass.contains(SrcReg) &&
RISCV::GPRRegClass.contains(DstReg)) {
Expand Down
6 changes: 6 additions & 0 deletions llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -47,14 +47,17 @@ define double @fminimum_f64(double %a, double %b) nounwind {
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
; RV32IZFINXZDINX-NEXT: mv a4, a2
; RV32IZFINXZDINX-NEXT: mv a5, a3
; RV32IZFINXZDINX-NEXT: bnez a6, .LBB0_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
; RV32IZFINXZDINX-NEXT: mv a4, a0
; RV32IZFINXZDINX-NEXT: mv a5, a1
; RV32IZFINXZDINX-NEXT: .LBB0_2:
; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
; RV32IZFINXZDINX-NEXT: bnez a6, .LBB0_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
; RV32IZFINXZDINX-NEXT: mv a0, a2
; RV32IZFINXZDINX-NEXT: mv a1, a3
; RV32IZFINXZDINX-NEXT: .LBB0_4:
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
Expand Down Expand Up @@ -121,14 +124,17 @@ define double @fmaximum_f64(double %a, double %b) nounwind {
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
; RV32IZFINXZDINX-NEXT: mv a4, a2
; RV32IZFINXZDINX-NEXT: mv a5, a3
; RV32IZFINXZDINX-NEXT: bnez a6, .LBB1_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
; RV32IZFINXZDINX-NEXT: mv a4, a0
; RV32IZFINXZDINX-NEXT: mv a5, a1
; RV32IZFINXZDINX-NEXT: .LBB1_2:
; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
; RV32IZFINXZDINX-NEXT: bnez a6, .LBB1_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
; RV32IZFINXZDINX-NEXT: mv a0, a2
; RV32IZFINXZDINX-NEXT: mv a1, a3
; RV32IZFINXZDINX-NEXT: .LBB1_4:
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
Expand Down
14 changes: 14 additions & 0 deletions llvm/test/CodeGen/RISCV/double-select-fcmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ define double @select_fcmp_oeq(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB1_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB1_2:
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
Expand Down Expand Up @@ -100,6 +101,7 @@ define double @select_fcmp_ogt(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB2_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB2_2:
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
Expand Down Expand Up @@ -146,6 +148,7 @@ define double @select_fcmp_oge(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB3_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB3_2:
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
Expand Down Expand Up @@ -192,6 +195,7 @@ define double @select_fcmp_olt(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB4_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB4_2:
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
Expand Down Expand Up @@ -238,6 +242,7 @@ define double @select_fcmp_ole(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB5_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB5_2:
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
Expand Down Expand Up @@ -288,6 +293,7 @@ define double @select_fcmp_one(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB6_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB6_2:
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
Expand Down Expand Up @@ -340,6 +346,7 @@ define double @select_fcmp_ord(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB7_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB7_2:
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
Expand Down Expand Up @@ -392,6 +399,7 @@ define double @select_fcmp_ueq(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB8_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB8_2:
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
Expand Down Expand Up @@ -440,6 +448,7 @@ define double @select_fcmp_ugt(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB9_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB9_2:
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
Expand Down Expand Up @@ -486,6 +495,7 @@ define double @select_fcmp_uge(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB10_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB10_2:
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
Expand Down Expand Up @@ -532,6 +542,7 @@ define double @select_fcmp_ult(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB11_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB11_2:
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
Expand Down Expand Up @@ -578,6 +589,7 @@ define double @select_fcmp_ule(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB12_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB12_2:
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
Expand Down Expand Up @@ -624,6 +636,7 @@ define double @select_fcmp_une(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB13_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB13_2:
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
Expand Down Expand Up @@ -674,6 +687,7 @@ define double @select_fcmp_uno(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB14_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB14_2:
; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
Expand Down

0 comments on commit 8c8abe6

Please sign in to comment.