Re-commit: r309094 [globalisel][tablegen] Fuse the generated tables t…

…ogether.

Summary:
Now that we have control flow in place, fuse the per-rule tables into a
single table. This is a compile-time saving at this point. However, this will
also enable the optimization of a table so that similar instructions can be
tested together, reducing the time spent on the matching the code.

This is NFC in terms of externally visible behaviour but some internals have
changed slightly. State.MIs is no longer reset between each rule that is
attempted because it's not necessary to do so. As a consequence of this the
restriction on the order that instructions are added to State.MIs has been
relaxed to only affect recorded instructions that require new elements to be
added to the vector. GIM_RecordInsn can now write to any element from 1 to
State.MIs.size() instead of just State.MIs.size().

The compile-time regressions from the last commit were caused by the ARM target
including a non-const variable (zero_reg) in the table and therefore generating
an initializer for it. That variable is now const.

Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar

Reviewed By: rovka

Subscribers: kristof.beyls, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D35681

llvm-svn: 309264

llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

@@ -58,7 +58,6 @@ bool InstructionSelector::executeMatchTable(
       // As an optimisation we require that MIs[0] is always the root. Refuse
       // any attempt to modify it.
       assert(NewInsnID != 0 && "Refusing to modify MIs[0]");
-      (void)NewInsnID;
 
       MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
       if (!MO.isReg()) {
@@ -74,9 +73,14 @@ bool InstructionSelector::executeMatchTable(
         break;
       }
 
-      assert((size_t)NewInsnID == State.MIs.size() &&
-             "Expected to store MIs in order");
-      State.MIs.push_back(MRI.getVRegDef(MO.getReg()));
+      MachineInstr *NewMI = MRI.getVRegDef(MO.getReg());
+      if ((size_t)NewInsnID < State.MIs.size())
+        State.MIs[NewInsnID] = NewMI;
+      else {
+        assert((size_t)NewInsnID == State.MIs.size() &&
+               "Expected to store MIs in order");
+        State.MIs.push_back(NewMI);
+      }
       DEBUG(dbgs() << CurrentIdx << ": MIs[" << NewInsnID
                    << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx
                    << ")\n");
@@ -213,7 +217,8 @@ bool InstructionSelector::executeMatchTable(
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       MachineOperand &OM = State.MIs[InsnID]->getOperand(OpIdx);
       if (!OM.isIntrinsicID() || OM.getIntrinsicID() != Value)
-        return false;
+        if (handleReject() == RejectAndGiveUp)
+          return false;
       break;
     }
     case GIM_CheckIsMBB: {

llvm/lib/Target/ARM/ARMInstructionSelector.cpp

@@ -98,7 +98,7 @@ createARMInstructionSelector(const ARMBaseTargetMachine &TM,
 }
 }
 
-unsigned zero_reg = 0;
+const unsigned zero_reg = 0;
 
 #define GET_GLOBALISEL_IMPL
 #include "ARMGenGlobalISel.inc"